TE28F010-150 데이터 시트보기 (PDF) - Intel

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TE28F010-150

28F010 1024K (128K X 8) CMOS FLASH MEMORY

Intel 

E

28F010

Start Erasure (4)

Y

Data = 00H?

N

Program All

Bytes to 00H

Bus

Operation

Command

Comments

Entire Memory Must = 00H

Before Erasure

Use Quick-Pulse

Programming Algorithm

(Figure 4)

Apply VPPH (1)

ADDR = 00H

PLSCNT = 0

Write Erase

Set-Up Cmd

Write Erase Cmd

Time Out 10 ms

Write Erase

Verify Cmd

Time Out 6 µs

Standby

Wait for VPP Ramp to VPPH (1)

Write

Write

Stand-by

Write

Standby

Initialize Addresses and

Pulse-Count

Set-Up

Erase

Data = 20H

Erase Data = 20H

Erase (2)

Verify

Duration of Erase Operation

(tWHWH2 )

Addr = Byte to Verify;

Data = A0H; Stops Erase

Operation(3)

tWHGL

Read Data

from Device

N

Data = FFH?

Increment Addr

Y

N

Last Address?

Y

Write Read Cmd

N

Inc

PLSCNT =

1000?

Y

Apply VPPL (1)

Apply VPPL (1)

Read

Standby

Read Byte to Verify Erasure

Compare Output to FFH

Increment Pulse-Count

Write

Read

Data = 00H, Resets the

Register for Read Operations

Standby

Wait for VPP Ramp to VPPL (1)

Erasure

Completed

Erase Error

0207_05

NOTES:

1. See DC Characteristics for the value of VPPH and VPPL.

2. Erase Verify is performed only after chip-erasure. A final read/compare may be performed (optional) after the register is

written with the Read command.

3. Refer to Principles of Operation.

4. CAUTION: The algorithm must be followed to ensure proper and reliable operation of the device.

Figure 5. 28F010 Quick-Erase Algorithm

15

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