MAX17411 데이터 시트보기 (PDF) - Maxim Integrated
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MAX17411
Maxim Integrated
MAX17411 Datasheet PDF : 72 Pages
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Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. VIN = 10V, VCC = VDDA = VDDB = 5V, EN = VCC, VGNDS_ = 0V, VFB_ = VCSP_AVE = VCSP_ = VCSN_ =
1V; [SerialVID = 1.00, FPWM MODE]; TA = -40°C to +105°C, unless otherwise noted. Specifications to -40NC and +105NC are guar-
anteed by design, not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Internal BST_ Switch On-
Resistance
DRVPWMA, DRVPWMB
Logic-High Voltage
RBST
BSTA1 to VDDA, BSTA2 to VDDA, BSTB to VDDB
VDD_ = 5V
ISOURCE = 3mA
VDD_
- 0.4
20
I
V
DRVPWMA, DRVPWMB
Logic-Low Voltage
ISINK = 3mA
0.4
V
LOGIC AND I/O
Enable Input High Voltage VEN_IH
0.67
Enable Input Low Voltage
VEN_IL
SERIALVID INTERFACE (per Intel SerialVID specification—see the Detailed Description)
V
0.33
V
SerialVID Input Low
Voltage (CLK, VDIO)
VIL
-0.1
+0.45
V
SerialVID Input High
Voltage (CLK, VDIO)
VIH
0.65
VTT +
1V
V
SerialVID Output Low Level
(VDIO, ALERT#)
VOL Open-drain pullup to VTT, RPU = 50I
0.36
V
SerialVID Open-Drain
Output On-Resistance
(VDIO, ALERT#, VRHOT#)
RON ISINK = 30mA, TA = 0°C to +105°C
4
13
I
SerialVID Logic Slew Rate
(CLK, VDIO, ALERT#)
0.5
2.0
V/ns
SerialVID Input Capacitance
CLK Frequency
CLK Absolute Min/Max
Period
CPAD
fCLK
Specified as a percentage of fCLK
4
pF
13
33.3 MHz
-5
+5
%
CLK High Time
CLK Low Time
Rise Time
Fall Time
Duty Cycle
tHIGH
tLOW
tRISE
tFALL
Specified as a percentage of tCLK period
Specified as a percentage of tCLK period
45
45
0.25
0.25
45
%
%
2.5
ns
2.5
ns
55
%
SerialVID Inactivity Timeout tRSTNA
0.14
0.40
Fs
Note 2: The equation for the target voltage VTARGET is:
VTARGET = the slew-rate-controlled version of either VDAC
where VDAC = 0V for shutdown, VDAC = VBOOT during startup, otherwise VDAC = VID (the VID voltages for all possible
VID codes are given in Table 3 and VOFFSET = the negative or positive offset to the output voltage based on the voltage
set from the offset register and the mode of operation (startup, shutdown, deeper sleep, or normal operation), as defined
elsewhere in this document.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ pin, with LX_ forced to 0V, BST_
forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-circuit
times may be different due to MOSFET switching speeds.
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