AD5543-EP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
CLK 1
SDI 2
RFB 3
VREF 4
AD5543-EP
TOP VIEW
(Not to Scale)
8 CS
7 VDD
6 GND
5 IOUT
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
CLK
Clock Input. Positive-edge triggered, clocks data into shift register.
2
SDI
Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored.
3
RFB
Internal Matching Feedback Resistor. This pin connects to an external op amp for voltage output.
4
VREF
DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.
5
IOUT
DAC Current Output. This pin connects to the inverting terminal of the external precision I-to-V op amp for
voltage output.
6
GND
Analog and Digital Ground.
7
VDD
Positive Power Supply Input. Specified range of operation at 5 V ± 10%.
8
CS
Chip Select. Active low digital input. Transfers shift-register data to DAC register on rising edge.
Rev. 0 | Page 6 of 12