ST90R40C6 데이터 시트보기 (PDF) - STMicroelectronics

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ST90R40C6

16K ROM HCMOS MCU WITH EEPROM, RAM AND A/D CONVERTER

STMicroelectronics 

ST9040

EEPROM (Continued)

1.3.2.7 EEPROM Control Register

EECR R241 (F1h) Page 0 Read/Write

(except EEBUSY: read only)

EEPROM Control Register

Reset value : 0000 0000b (00h)

7

0

0 VERIFY EESTBY EEIEN PLLST PLLEN EEBUSY EEWEN

bit 7 = B7: This bit is forced to “0” after reset and

MUST not be modified by the user.

bit 6 = VERIFY: Set Verify mode. Verify (active

high) is used to activate the verify mode.

The verify mode provides a guarentee of good re-

tention of the programmed bit. When active, the

reading voltage on the cell gate is decreased from

1.2V to 0.0V, decreasing the current from the pro-

grammed cell by 20%. If the cell is well pro-

grammed (to “1”), a “1” will still be read, otherwise

a “0” will be read.

Note . The verify mode must not be used during an

erasing or a programming cycle).

bit 5 = EESTBY: EEPROM Stand-By. EESTBY =

“1” switches off all power consumption sources in-

side the EEPROM. Any attempt to access the

EEPROM when EESTBY = “1” will produce unpre-

dictable results.

Table 1-5. Register Map Addendum

Note. After EESTBY is reset, the user must wait 6

CPUCLK cycles (e.g. 1 nop instruction) before se-

lecting the EEPROM.

bit 4 = EEIEN: EEPROM Interrupt Enable. INTEN

= “1” disables the external interrupt source INT4,

and enables the EEPROM to send its interrupt re-

quest to the central interrupt unit at the end of each

write procedure.

bit 3 = PLLST: Parallel Write Start. Setting PLLST

to “1” starts the parallel writing procedure.It can be

set only if PLLEN is alreadyset. PLLST is internally

reset at the end of the programming sequence.

bit 2 = PLLEN: Parallel write Enable. Setting

PLLEN to “1” enables the parallel writing mode

which allows the user to write up to 16 bytes at the

same time. PLLEN is internally reset at the end of

the programming sequence.

bit 1 = EEBUSY: BUSY. When this read only bit is

high, an EEPROM write operation is in progress

and any attempt to access the EEPROM is

aborted.

bit 0 = EEWEN: EEPROM Write Enable. Setting

this bit allows programming of the EEPROM, when

low a writing attempt has no effect.

1.3.3 REGISTER MAP

Please refer to the Register Map of the ST9036 for

all general registers with the exceptionof the regis-

ter shown in the following table.

EECR R241

(F1h)

Page 0 Read/Write

Control Registers

Figure 1-5. EEPROM Parallel Programming Rows

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