SST25PF040B
CE#
MODE 3
SCK MODE 0
0 1 23456 78
15 16
23 24 31
SI
D8
ADDR ADDR ADDR
MSB
MSB
SO
HIGH IMPEDANCE
25134 63KBlkEr.0
FIGURE 4-12:
64-KBYTE BLOCK-ERASE SEQUENCE
4.4.9 CHIP-ERASE
The Chip-Erase instruction clears all bits in the device
to FFH. A Chip-Erase instruction will be ignored if any
of the memory area is protected. Prior to any Write oper-
ation, the Write-Enable (WREN) instruction must be exe-
cuted. CE# must remain active low for the duration of
the Chip-Erase instruction sequence. The Chip-Erase
instruction is initiated by executing an 8-bit command,
60H or C7H. CE# must be driven high before the instruction
is executed. The user may poll the Busy bit in the software
status register or wait TCE for the completion of the
internal self-timed Chip-Erase cycle. See Figure 4-13
for the Chip-Erase sequence.
CE#
MODE 3
SCK MODE 0
0 1 23456 7
FIGURE 4-13:
SI
60 or C7
MSB
SO
HIGH IMPEDANCE
25134 ChEr.0
CHIP-ERASE SEQUENCE
2012 Microchip Technology Inc.
DS25134A-page 13