HEF4046B(2016) 데이터 시트보기 (PDF) - NXP Semiconductors.

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HEF4046B
(Rev.:2016)

Phase-locked loop

NXP Semiconductors. 

Nexperia

HEF4046B

Phase-locked loop



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DDH



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DDH













 









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Line (1): VDD = 5 V;

Line (2): VDD = 10 V, 15 V.

Fig 9. Typical ratio of R2/R1 as a function of the ratio

fmax/fmin

R2 = ; VCO_IN at 0.5VDD; CL = 50 pF.

Lines (1) and (2): VDD = 15 V;

Lines (3) and (4): VDD = 10 V;

Lines (5) and (6): VDD = 5 V;

Lines (1), (3), and (5): C1 = 50 pF;

Lines (2), (4), and (6): C1 = 1 F.

Fig 10. Power dissipation as a function of R1



3

—:



DDH



























5Nȍ

R1 = ; VCO_IN at VSS (0 V); CL = 50 pF.

Lines (1) and (2): VDD = 15 V;

Lines (3) and (4): VDD = 10 V;

Lines (5) and (6): VDD = 5 V;

Lines (1), (3), and (5): C1 = 50 pF;

Lines (2), (4), and (6): C1 = 1 F.

Fig 11. Power dissipation as a function of R2



3

—:







DDH

















56)Nȍ

VCO_IN at 0.5VDD; R1 = ; R2 = .

Line (1): VDD = 15 V;

Line (2): VDD = 10 V;

Line (3): VDD = 5 V.

Fig 12. Power dissipation of source follower as a

function of RL

HEF4046B

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 24 March 2016

© Nexperia B.V. 2017. All rights reserved

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