NXP Semiconductors
HEF4046B
Phase-locked loop
f
fmax
f2
fo
fo'
f1
ΔV
ΔV
1/2VDD
VVCO IN
VDD
001aae638
See Section 10.
For VCO linearity:
f0
=
-f-1----+-----f--2-
2
linearity = f----0--f--–-0----f-0- 100 %
This figure and the above formula also apply to source follower linearity: substitute VO at SF_OUT for f.
V = 0.3 V at VDD = 5 V;
V = 2.5 V at VDD = 10 V;
V = 5.0 V at VDD = 15 V.
Fig 13. Definition of linearity
HEF4046B
Product data sheet
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Rev. 5 — 18 November 2011
© NXP B.V. 2011. All rights reserved.
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