CY7C1383D-133BZC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1383D-133BZC Datasheet PDF : 29 Pages
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CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Pin Definitions (continued)
Name
MODE
VDD
VDDQ
VSS
VSSQ
TDO
TDI
TMS
TCK
NC
IO
Description
Input-Static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.
Power Supply Power supply inputs to the core of the device.
IO Power Supply Power supply for the IO circuitry.
Ground
Ground for the core of the device.
IO Ground Ground for the IO circuitry.
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous JTAG feature is not being utilized, this pin can be left unconnected. This pin is not available
on TQFP packages.
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be left floating or connected to VDD through a pull up
resistor. This pin is not available on TQFP packages.
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
JTAG-
Clock
–
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G
are address expansion pins and are not internally connected to the die.
VSS/DNU
Ground/DNU This pin can be connected to ground or can be left floating.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133 MHz device).
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
supports secondary cache in systems utilizing a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium® and i486™ processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3 [2]) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 [2] are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter and/or control logic, and later presented to the
memory core. If the OE input is asserted LOW, the requested
data will be available at the data outputs with a maximum to
tCDV after clock rise. ADSP is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 [2] are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX) are ignored during this first clock
cycle. If the write inputs are asserted active (see Truth Table
for Read/Write [4, 9] on page 10 for appropriate states that
indicate a write) on the next clock rise, the appropriate data will
be latched and written into the device. Byte writes are allowed.
All IOs are tri-stated during a byte write. As this is a common
IO device, the asynchronous OE input signal must be
Document #: 38-05544 Rev. *F
Page 7 of 29
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