KSZ9021GN 데이터 시트보기 (PDF) - Micrel

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KSZ9021GN

Gigabit Ethernet Transceiver with GMII / MII Support

Micrel 

Micrel, Inc.

KSZ9021GN

Strapping Options

Pin Number

48

17

19

Pin Name

PHYAD2

PHYAD1

PHYAD0

39

MODE3

41

MODE2

43

MODE1

44

MODE0

45

CLK125_EN

55

LED_MODE

Type(1)

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Pin Function

The PHY Address, PHYAD[2:0], is latched at power-up / reset and is configurable to

any value from 1 to 7. Each PHY address bit is configured as follows:

Pull-up = 1

Pull-down = 0

PHY Address bits [4:3] are always set to ‘00’.

The MODE[3:0] strap-in pins are latched at power-up / reset and are defined as

follows:

MODE[3:0]

Mode

0000

Reserved – not used

0001

GMII / MII Mode

0010

Reserved – not used

0011

Reserved – not used

0100

NAND Tree Mode

0101

Reserved – not used

0110

Reserved – not used

0111

Chip Power Down Mode

1000

Reserved – not used

1001

Reserved – not used

1010

Reserved – not used

1011

Reserved – not used

1100

Reserved – not used

1101

Reserved – not used

1110

Reserved – not used

1111

Reserved – not used

CLK125_EN is latched at power-up / reset and is defined as follows:

Pull-up = Enable 125MHz Clock Output

Pull-down = Disable 125MHz Clock Output

Pin 55 (CLK125_NDO) provides the 125MHz reference clock output option for use by

the MAC.

LED_MODE is latched at power-up / reset and is defined as follows:

Pull-up = Single LED Mode

Pull-down = Tri-color Dual LED Mode

Note:

1. I/O = Bi-directional.

Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during

power-up or reset, and consequently cause the PHY strap-in pins on the GMII/MII signals to be latched to the incorrect

configuration. In this case, it is recommended to add external pull-ups/pull-downs on the PHY strap-in pins to ensure

the PHY is configured to the correct pin strap-in mode.

September 2010

14

M9999-091010-1.1

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