V363EPC 데이터 시트보기 (PDF) - QuickLogic Corporation
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V363EPC Datasheet PDF : 23 Pages
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AC Specifications
Local Bus Timings
Table 17: Local Bus Timing Parameters for VCC = 3.3 Volts ± 10%
# Symbol
Description
Notes Min Max Units
1 TC
2 TCH
3 TCL
4 TSU
LCLK/MEMCLK period
LCLK/MEMCLK high time
LCLK/MEMCLK low time
Synchronous input setup
20
ns
1
9
ns
2
9
ns
3
6
ns
4a TSU
Synchronous input setup (AS/ADS/LREQ)
4
ns
4b TSU
Synchronous input setup for HOLDA (LBGRT)
3
ns
5 TH
6 TCOV
Synchronous input hold
LCLK/MEMCLK to output valid delay
2
ns
4
4 11 ns
6a TCOV LCLK/MEMCLK to output valid delay (address, data)
4 12 ns
7 TCZO
8 TCOZ
LCLK/MEMCLK to output driving delay
LCLK/MEMCLK to output float delay
4 11 ns
5
4 11 ns
9 TRST
Reset period when LRST used as input
16 TC
ns
1. Measured at 1.5 V.
2. Measured at 1.5 V.
3. All local bus signals except those in 4a and 4b.
4. All local bus signals except those in 6a.
5. READY, BLAST, ADS are driven to high impedance at the falling edge of LCLK.
Table 18: PCI Bus Timing Parameters for VCC = 3.3 Volts ± 10%
# Symbol
Description
1
TC
2
TSU
2a TSU
3
TH
4 TCOV
4a TCOV
5 TCZO
6 TCOZ
7 TRST
PCLK period
Synchronous input setup to PCLK
Synchronous input setup to PCLK (GNT)
Synchronous input hold from PCLK
PCLK to output valid delay
PCLK to output valid delay (REQ)
PCLK to output driving delay
PCLK to output float delay
Reset period when PRST used as input
1. All PCI bus signals except those in 2a.
2. All PCI bus signals except those in 4a.
Notes Min Max Units
20
ns
1
7
ns
9
ns
0
ns
2
3
11 ns
3
12 ns
3
11 ns
4
18 ns
16 TC
© 2000 V3 Semiconductor Corp.
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
21
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