STM8AP528A 데이터 시트보기 (PDF) - STMicroelectronics
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STM8AP528A Datasheet PDF : 125 Pages
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STM8AF526x/8x/Ax STM8AF6269/8x/Ax
Revision history
Date
30-Jan-2011
18-Jul-2012
Table 55. Document revision history (continued)
Revision
Changes
8
(continued)
Removed note 1 in Table 24: General operating conditions and note
1 below Figure 11: fCPUmax versus VDD.
Removed note 3 in Table 26: Total current consumption in Run, Wait
and Slow mode. General conditions for VDD apply, TA = -40 °C to
150 °C.
Removed note 2 in Table 31: HSE external clock characteristics and
Table 35: Flash program memory/data EEPROM memory
Removed note 1 in Table 37: Data memory. Modified TWE maximum
value in Table 36: Flash program memory and Table 37: Data
memory.
Added tIFP(NRST) and renamed VF(NRST) tIFP in Table 39: NRST pin
characteristics.
Added recommendation concerning NRST pin level, and power
consumption sensitive applications, above Figure 39:
Recommended reset pin protection, and updated external capacitor
value.
Updated Note 1 in Table 40: TIM 1, 2, 3, and 4 electrical
specifications.
Updated Note 1 in Table 41: SPI characteristics.
Moved know limitations to separate errata sheet.
Added “not recommended for new design” note to device family 51,
memory size 7 and 9, and temperature range B, in Figure 60:
STM8AF526x/8x/Ax and STM8AF6269/8x/Ax ordering information
scheme1.
Added Raisonance compiler in Section 13.2: Software tools.
Updated wildcards of document part numbers.
Added VFQFPN package.
Added STM8AF62A6 part number.
Table 1: Device summary updated footnote 1 and added footnote 2.
Table: STM8AF52xx product line-up with CAN and Table:
STM8AF62xx product line-up without CAN: added “P” version for all
order codes; updated size of data EEPROM for 64K devices to 2K
instead of 1.5K; updated RAM.
Figure 1: STM8AF526x/8x/Ax and STM8AF6269/8x/Ax block
diagram: updated POR, BOR and WDG; removed PDR; added
legend.
9
Section 5.4: Flash program and data EEPROM: removed non
relevant bullet points and added a sentence about the factory
program.
Added Table 4: Peripheral clock gating bits (CLK_PCKENR1) and
updated Table 5: Peripheral clock gating bits (CLK_PCKENR2)
Section : ADC features: updated ADC input range.
Table 12: Memory model 128K: updated RAM size, RAM end
addresses, and stack roll-over addresses; updated footnote 1
Table 18: Option bytes: updated factory default setting for NOPT17;
updated footnotes.
Table 20: Voltage characteristics: updated VDDX - VDD to VDDX - VSS.
Table 24: General operating conditions: updated VCAP.
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