DHQ1ETSSR1VB 데이터 시트보기 (PDF) - Intel
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DHQ1ETSSR1VB Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—
14.5.11Capabilities List Pointer (CAPP)—Offset 34h.............................................. 270
14.5.12Bridge Control (INTR_BCTRL)—Offset 3Ch................................................ 271
14.5.13PCI Express Capabilities (CLIST_XCAP)—Offset 40h................................... 272
14.5.14Device Capabilities (DCAP)—Offset 44h.................................................... 273
14.5.15Device Status (DCTL_DSTS)—Offset 48h ................................................. 274
14.5.16Link Capabilities (LCAP)—Offset 4Ch........................................................ 275
14.5.17Link Status (LCTL_LSTS)—Offset 50h ...................................................... 277
14.5.18Slot Capabilities (SLCAP)—Offset 54h ...................................................... 278
14.5.19Slot Status (SLCTL_SLSTS)—Offset 58h................................................... 279
14.5.20Root Control (RCTL)—Offset 5Ch............................................................. 281
14.5.21Root Status (RSTS)—Offset 60h.............................................................. 281
14.5.22Device Capabilities 2 (DCAP2)—Offset 64h ............................................... 282
14.5.23Device Status 2 (DCTL2_DSTS2)—Offset 68h ........................................... 283
14.5.24Link Capability 2 (LCAP2)—Offset 6Ch ..................................................... 284
14.5.25Link Status 2 (LCTL2_LSTS2)—Offset 70h ................................................ 284
14.5.26Slot Capabilities 2 (SLCAP2)—Offset 74h.................................................. 286
14.5.27Slot Status 2 (SLCTL2_SLSTS2)—Offset 78h............................................. 286
14.5.28Message Signaled Interrupt Message Control (MID_MC)—Offset 80h............ 287
14.5.29Message Signaled Interrupt Message Address (MA)—Offset 84h .................. 287
14.5.30Message Signaled Interrupt Message Data (MD)—Offset 88h ...................... 288
14.5.31Subsystem Vendor Capability (SVCAP)—Offset 90h ................................... 288
14.5.32Subsystem Vendor IDs (SVID)—Offset 94h .............................................. 289
14.5.33PCI Power Management Capabilities (PMCAP_PMC)—Offset A0h .................. 289
14.5.34PCI Power Management Control And Status (PMCS)—Offset A4h ................. 290
14.5.35Channel Configuration (CCFG)—Offset D0h .............................................. 291
14.5.36Miscellaneous Port Configuration 2 (MPC2)—Offset D4h ............................. 292
14.5.37Miscellaneous Port Configuration (MPC)—Offset D8h .................................. 293
14.5.38SMI / SCI Status (SMSCS)—Offset DCh ................................................... 294
14.5.39Message Bus Control (PHYCTL_PHYCTL2_IOSFSBCTL)—Offset F4h .............. 295
14.5.40Advanced Error Reporting Capability Header (AECH)—Offset 100h............... 296
14.5.41Uncorrectable Error Status (UES)—Offset 104h ......................................... 297
14.5.42Uncorrectable Error Mask (UEM)—Offset 108h .......................................... 298
14.5.43Uncorrectable Error Severity (UEV)—Offset 10Ch ...................................... 299
14.5.44Correctable Error Status (CES)—Offset 110h ............................................ 300
14.5.45Correctable Error Mask (CEM)—Offset 114h.............................................. 301
14.5.46Advanced Error Capabilities and Control (AECC)—Offset 118h ..................... 302
14.5.47Header Log (HL_DW1)—Offset 11Ch........................................................ 302
14.5.48Header Log (HL_DW2)—Offset 120h........................................................ 303
14.5.49Header Log (HL_DW3)—Offset 124h........................................................ 303
14.5.50Header Log (HL_DW4)—Offset 128h........................................................ 303
14.5.51Root Error Command (REC)—Offset 12Ch ................................................ 304
14.5.52Root Error Status (RES)—Offset 130h ...................................................... 304
14.5.53Error Source Identification (ESID)—Offset 134h ........................................ 305
15.0 10/100 Mbps Ethernet ........................................................................................... 307
15.1 Signal Descriptions .......................................................................................... 307
15.2 Features:........................................................................................................ 307
15.3 References...................................................................................................... 308
15.4 Register Map................................................................................................... 309
15.5 PCI Configuration Registers............................................................................... 309
15.5.1 Vendor ID (VENDOR_ID)—Offset 0h ........................................................ 310
15.5.2 Device ID (DEVICE_ID)—Offset 2h .......................................................... 311
15.5.3 Command Register (COMMAND_REGISTER)—Offset 4h .............................. 311
15.5.4 Status Register (STATUS)—Offset 6h....................................................... 312
15.5.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .................. 313
Intel® Quark SoC X1000
DS
10
October 2013
Document Number: 329676-001US
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