DHQ1ETSSR1VB 데이터 시트보기 (PDF) - Intel

부품명

상세내역

제조사

DHQ1ETSSR1VB

Intel® Quark SoC X1000

Intel 

—Intel® Quark SoC X1000

15.6

15.5.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ...................................... 313

15.5.7 Latency Timer (LATENCY_TIMER)—Offset Dh ........................................... 313

15.5.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 314

15.5.9 BIST (BIST)—Offset Fh ......................................................................... 314

15.5.10Base Address Register (BAR0)—Offset 10h .............................................. 315

15.5.11Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ...................... 315

15.5.12Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch....................... 316

15.5.13Subsystem ID (SUB_SYS_ID)—Offset 2Eh ............................................... 316

15.5.14Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h.............. 316

15.5.15Capabilities Pointer (CAP_POINTER)—Offset 34h....................................... 317

15.5.16Interrupt Line Register (INTR_LINE)—Offset 3Ch ...................................... 317

15.5.17Interrupt Pin Register (INTR_PIN)—Offset 3Dh ......................................... 318

15.5.18MIN_GNT (MIN_GNT)—Offset 3Eh .......................................................... 318

15.5.19MAX_LAT (MAX_LAT)—Offset 3Fh ........................................................... 318

15.5.20Capability ID (PM_CAP_ID)—Offset 80h................................................... 319

15.5.21Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ........................... 319

15.5.22Power Management Capabilities (PMC)—Offset 82h ................................... 319

15.5.23Power Management Control/Status Register (PMCSR)—Offset 84h .............. 320

15.5.24PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h ..... 321

15.5.25Power Management Data Register (DATA_REGISTER)—Offset 87h .............. 321

15.5.26Capability ID (MSI_CAP_ID)—Offset A0h ................................................. 322

15.5.27Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h .......................... 322

15.5.28Message Control (MESSAGE_CTRL)—Offset A2h ....................................... 322

15.5.29Message Address (MESSAGE_ADDR)—Offset A4h ..................................... 323

15.5.30Message Data (MESSAGE_DATA)—Offset A8h .......................................... 323

15.5.31Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ...................................... 324

15.5.32Pending Bits for MSI (PER_VEC_PEND)—Offset B0h .................................. 324

Memory Mapped Registers................................................................................ 325

15.6.1 MAC Configuration Register (Register 0) (GMAC_REG_0)—Offset 0h............ 329

15.6.2 MAC Frame Filter (Register 1) (GMAC_REG_1)—Offset 4h .......................... 332

15.6.3 Hash Table High Register (Register 2) (GMAC_REG_2)—Offset 8h ............... 334

15.6.4 Hash Table Low Register (Register 3) (GMAC_REG_3)—Offset Ch ............... 334

15.6.5 GMII Address Register (Register 4) (GMAC_REG_4)—Offset 10h ................. 335

15.6.6 GMII Data Register (Register 5) (GMAC_REG_5)—Offset 14h ..................... 336

15.6.7 Flow Control Register (Register 6) (GMAC_REG_6)—Offset 18h .................. 337

15.6.8 VLAN Tag Register (Register 7) (GMAC_REG_7)—Offset 1Ch ...................... 338

15.6.9 Version Register (Register 8) (GMAC_REG_8)—Offset 20h ......................... 339

15.6.10Debug Register (Register 9) (GMAC_REG_9)—Offset 24h........................... 340

15.6.11Interrupt Register (Register 14) (GMAC_REG_14)—Offset 38h.................... 341

15.6.12Interrupt Mask Register (Register 15) (GMAC_REG_15)—Offset 3Ch ........... 342

15.6.13MAC Address0 High Register (Register 16) (GMAC_REG_16)—Offset 40h ..... 343

15.6.14MAC Address0 Low Register (Register 17) (GMAC_REG_17)—Offset 44h ...... 343

15.6.15MMC Control Register (Register 64) (GMAC_REG_64)—Offset 100h ............. 344

15.6.16MMC Receive Interrupt Register (MMC_INTR_RX)—Offset 104h .................. 345

15.6.17MMC Transmit Interrupt Register (MMC_INTR_TX)—Offset 108h ................. 347

15.6.18MMC Receive Interrupt Mask Register (MMC_INTR_MASK_RX)—Offset 10Ch 349

15.6.19MMC Transmit Interrupt Mask Register (MMC_INTR_MASK_TX)—Offset 110h 351

15.6.20MMC Transmit Good Bad Octet Counter Register

(TXOCTETCOUNT_GB)—Offset 114h........................................................ 353

15.6.21MMC Transmit Good Bad Frame Counter Register

(TXFRAMECOUNT_GB)—Offset 118h ....................................................... 353

15.6.22MMC Transmit Broadcast Good Frame Counter Register

(TXBROADCASTFRAMES_G)—Offset 11Ch................................................ 354

15.6.23MMC Transmit Multicast Good Frame Counter Register

(TXMULTICASTFRAMES_G)—Offset 120h ................................................. 354

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

11

Share Link: