DHQ1ETSSR1VB 데이터 시트보기 (PDF) - Intel
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DHQ1ETSSR1VB Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—
4.8 General Interface Timing ....................................................................................78
4.8.1 Legacy SPI Interface Timing.....................................................................78
4.8.2 SPI0/1 Interface Timing...........................................................................78
4.8.3 SDIO Interface Timing.............................................................................79
4.9 Clock AC Timing ................................................................................................80
4.9.1 Reference Clock AC Characteristics............................................................80
5.0 Register Access Methods.........................................................................................83
5.1 Fixed I/O Register Access ...................................................................................83
5.2 Fixed Memory Mapped Register Access .................................................................83
5.3 I/O Referenced Register Access ...........................................................................83
5.4 Memory Referenced Register Access.....................................................................84
5.5 PCI Configuration Register Access ........................................................................84
5.5.1 PCI Configuration Access - CAM: I/O Indexed Scheme .................................84
5.5.2 PCI Configuration Access - ECAM: Memory Mapped Scheme .........................85
5.6 Message Bus Register Access ..............................................................................86
5.7 Register Field Access Types.................................................................................87
6.0 Mapping Address Spaces..........................................................................................89
6.1 Physical Address Space Mappings.........................................................................89
6.1.1 Bridge Memory Map ................................................................................89
6.1.1.1 MMIO ......................................................................................91
6.1.1.2 DOS DRAM ...............................................................................92
6.1.1.3 Additional Mappings...................................................................92
6.1.2 MMIO Map .............................................................................................93
6.2 I/O Address Space .............................................................................................93
6.2.1 Host Bridge I/O Map ...............................................................................94
6.2.2 I/O Fabric I/O Map..................................................................................94
6.2.2.1 Legacy Bridge Fixed I/O Address Ranges ......................................94
6.2.2.2 Variable I/O Address Ranges.......................................................94
6.3 PCI Configuration Space .....................................................................................95
6.4 Message Bus Space............................................................................................97
7.0 Clocking ...................................................................................................................99
7.1 Clocking Features ..............................................................................................99
7.2 Platform/System Clock Domains ........................................................................ 100
8.0 Power Management ............................................................................................... 103
8.1 Power Management Features............................................................................. 103
8.2 ACPI Supported States ..................................................................................... 103
8.2.1 S-State Definition ................................................................................. 103
8.2.1.1
8.2.1.2
8.2.1.3
8.2.1.4
S0 - Full On ............................................................................ 103
S3 - Suspend to RAM (Standby) ................................................ 103
S4 - Suspend to Disk (Hibernate) .............................................. 103
S5 - Soft Off ........................................................................... 104
8.2.2 System States...................................................................................... 104
8.2.3 Processor Idle States............................................................................. 105
8.2.4 Integrated Memory Controller States ....................................................... 105
8.2.5 PCIe* States ........................................................................................ 105
8.2.6 Interface State Combinations ................................................................. 106
8.3 Processor Core Power Management .................................................................... 106
8.3.1 Low-Power Idle States........................................................................... 106
8.3.1.1 Clock Control and Low-Power States .......................................... 106
8.3.2 Processor Core C-States Description........................................................ 106
8.3.2.1 Core C0 State ......................................................................... 106
8.3.2.2 Core C1 State ......................................................................... 107
8.3.2.3 Core C2 State ......................................................................... 107
Intel® Quark SoC X1000
DS
4
October 2013
Document Number: 329676-001US
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