DHQ1ETSSR1VB 데이터 시트보기 (PDF) - Intel
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DHQ1ETSSR1VB Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
8.4 Memory Controller Power Management............................................................... 107
8.4.1 Disabling Unused System Memory Outputs .............................................. 107
8.4.2 DRAM Power Management and Initialization ............................................. 107
8.4.2.1 Initialization Role of CKE .......................................................... 107
8.4.2.2 Dynamic Self-Refresh .............................................................. 107
8.4.2.3 Dynamic Power Down Operation ............................................... 108
8.4.2.4 Functional Clock Gating ........................................................... 108
9.0 Power Up and Reset Sequence............................................................................... 109
9.1 Intel® Quark SoC X1000 System States ............................................................. 109
9.1.1 System Sleeping States Control (S-States) .............................................. 109
9.2 Power Up and Down Sequences......................................................................... 109
9.2.1 Power Up, Wake and Reset Overview ...................................................... 109
9.2.2 RTC Power Well Transition: G5 to G3 State Transition ............................... 110
9.2.3 Power-Up Sequence without G2/G3: No Coin-Cell Battery .......................... 111
9.2.4 AC Power Applied: G3 to S4/S5 State Transition ....................................... 112
9.2.5 Using PWR_BTN: Transition from S4/S5 to S0 .......................................... 112
9.2.6 Going to Sleep: Transitions from S0 to S3 or S4/S5 .................................. 116
9.2.7 Wake Events: Transition from S3 to S0 ................................................... 116
9.2.8 System Reset Sequences....................................................................... 116
9.2.8.1 Cold Boot Sequence ............................................................... 117
9.2.8.2 Cold Reset Sequence............................................................... 117
9.2.8.3 Warm Reset Sequence (Internal) .............................................. 117
9.2.8.4 Externally Initiated Warm Reset Sequence ................................. 117
9.2.9 Handling Power Failures ........................................................................ 117
10.0 Thermal Management ............................................................................................ 119
10.1 Overview ....................................................................................................... 119
10.2 Thermal Sensor............................................................................................... 119
11.0 Processor Core ...................................................................................................... 121
12.0 Host Bridge ........................................................................................................... 123
12.1 Embedded SRAM (eSRAM)................................................................................ 123
12.1.1 Initialization ........................................................................................ 123
12.1.2 Configuration....................................................................................... 123
12.1.2.1 4KB Page Mode ...................................................................... 123
12.1.2.2 512KB Block Page Mode........................................................... 124
12.1.3 Configuration Locking ........................................................................... 125
12.1.4 ECC Protection ..................................................................................... 126
12.1.5 Flush to DRAM ..................................................................................... 126
12.2 Isolated Memory Regions (IMR)......................................................................... 126
12.2.1 IMR Violation ....................................................................................... 127
12.2.2 IMR Locking......................................................................................... 127
12.3 Remote Management Unit DMA ......................................................................... 127
12.3.1 ECC Scrubbing .................................................................................... 128
12.4 Register Map .................................................................................................. 128
12.5 PCI Configuration Registers .............................................................................. 129
12.5.1 PCI Device ID and Vendor ID Fields (PCI_DEVICE_VENDOR)—Offset 0h....... 129
12.5.2 PCI Status and Command Fields (PCI_STATUS_COMMAND)—Offset 4h ........ 129
12.5.3 PCI Class Code and Revision ID Fields (PCI_CLASS_REVISION)—Offset 8h... 130
12.5.4 PCI Miscellaneous Fields (PCI_MISC)—Offset Ch ....................................... 130
12.5.5 PCI Subsystem ID and Subsystem Vendor ID Fields
(PCI_SUBSYSTEM)—Offset 2Ch .............................................................. 131
12.5.6 Message Bus Control Register (MCR) (SB_PACKET_REG)—Offset D0h.......... 132
12.5.7 Message Data Register (MDR) (SB_DATA_REG)—Offset D4h ...................... 132
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
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