DHQ1ETSSR1VB 데이터 시트보기 (PDF) - Intel
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DHQ1ETSSR1VB Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
12.7.2.22MTRR Fixed 4KB Range 0xE0000 (MTRR_FIX4K_E0000)—Offset
50h....................................................................................... 156
12.7.2.23MTRR Fixed 4KB Range 0xE4000 (MTRR_FIX4K_E4000)—Offset
51h....................................................................................... 157
12.7.2.24MTRR Fixed 4KB Range 0xE8000 (MTRR_FIX4K_E8000)—Offset
52h....................................................................................... 157
12.7.2.25MTRR Fixed 4KB Range 0xEC000 (MTRR_FIX4K_EC000)—Offset
53h....................................................................................... 158
12.7.2.26MTRR Fixed 4KB Range 0xF0000 (MTRR_FIX4K_F0000)—Offset
54h....................................................................................... 158
12.7.2.27MTRR Fixed 4KB Range 0xF4000 (MTRR_FIX4K_F4000)—Offset
55h....................................................................................... 159
12.7.2.28MTRR Fixed 4KB Range 0xF8000 (MTRR_FIX4K_F8000)—Offset
56h....................................................................................... 160
12.7.2.29MTRR Fixed 4KB Range 0xFC000 (MTRR_FIX4K_FC000)—Offset
57h....................................................................................... 160
12.7.2.30System Management Range Physical Base
(MTRR_SMRR_PHYSBASE)—Offset 58h ...................................... 161
12.7.2.31System Management Range Physical Mask
(MTRR_SMRR_PHYSMASK)—Offset 59h...................................... 161
12.7.2.32MTRR Variable Range Physical Base 0
(MTRR_VAR_PHYSBASE0)—Offset 5Ah....................................... 162
12.7.2.33MTRR Variable Range Physical Mask 0 (MTRR_VAR_PHYSMASK0)—
Offset 5Bh ............................................................................. 162
12.7.2.34MTRR Variable Range Physical Base 1
(MTRR_VAR_PHYSBASE1)—Offset 5Ch....................................... 163
12.7.2.35MTRR Variable Range Physical Mask 1 (MTRR_VAR_PHYSMASK1)—
Offset 5Dh ............................................................................. 164
12.7.2.36MTRR Variable Range Physical Base 2
(MTRR_VAR_PHYSBASE2)—Offset 5Eh ....................................... 164
12.7.2.37MTRR Variable Range Physical Mask 2 (MTRR_VAR_PHYSMASK2)—
Offset 5Fh.............................................................................. 165
12.7.2.38MTRR Variable Range Physical Base 3
(MTRR_VAR_PHYSBASE3)—Offset 60h ....................................... 165
12.7.2.39MTRR Variable Range Physical Mask 3 (MTRR_VAR_PHYSMASK3)—
Offset 61h ............................................................................. 166
12.7.2.40MTRR Variable Range Physical Base 4
(MTRR_VAR_PHYSBASE4)—Offset 62h ....................................... 166
12.7.2.41MTRR Variable Range Physical Mask 4 (MTRR_VAR_PHYSMASK4)—
Offset 63h ............................................................................. 167
12.7.2.42MTRR Variable Range Physical Base 5
(MTRR_VAR_PHYSBASE5)—Offset 64h ....................................... 168
12.7.2.43MTRR Variable Range Physical Mask 5 (MTRR_VAR_PHYSMASK5)—
Offset 65h ............................................................................. 168
12.7.2.44MTRR Variable Range Physical Base 6
(MTRR_VAR_PHYSBASE6)—Offset 66h ....................................... 169
12.7.2.45MTRR Variable Range Physical Mask 6 (MTRR_VAR_PHYSMASK6)—
Offset 67h ............................................................................. 169
12.7.2.46MTRR Variable Range Physical Base 7
(MTRR_VAR_PHYSBASE7)—Offset 68h ....................................... 170
12.7.2.47MTRR Variable Range Physical Mask 7 (MTRR_VAR_PHYSMASK7)—
Offset 69h ............................................................................. 170
12.7.3 Remote Management Unit (Port 0x04) .................................................... 171
12.7.3.1 ECC Scrubber Configuration Register (P_CFG_50)—Offset 50h ...... 171
12.7.3.2 SPI DMA Count Register (P_CFG_60)—Offset 60h........................ 172
12.7.3.3 SPI DMA Destination Register (P_CFG_61)—Offset 61h ................ 173
12.7.3.4 SPI DMA Source Register (P_CFG_62)—Offset 62h ...................... 173
12.7.3.5 Processor Register Block (P_BLK) Base Address
(P_CFG_70)—Offset 70h .......................................................... 174
12.7.3.6 Control Register (P_CFG_71)—Offset 71h................................... 174
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
7
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