Figure 2-16. Per Region Secondary Clock Selection
Architecture
LatticeECP3 Family Data Sheet
Secondary Clock Feedlines: 6 PIOs + 16 Routing
8:1
8:1
8:1
8:1
8:1
8:1
8:1
8:1
SC0
SC1
SC2
SC3
SC4
SC5
SC6
SC7
8 Secondary Clocks (SC0 to SC7) per Region
Clock/Control
Slice Clock Selection
Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All
the primary clocks and seven secondary clocks are routed to this clock selection mux. Other signals can be used
as a clock input to the slices via routing. Slice controls are generated from the secondary clocks/controls or other
signals connected via routing.
If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-17. Slice0 through Slice2 Clock Selection
Primary Clock
8
Secondary Clock
7
Routing
12
Vcc
1
Figure 2-18. Slice0 through Slice2 Control Selection
Clock to Slice
28:1
Secondary Control
5
Routing
14
Vcc
1
Slice Control
20:1
2-16