CS42L56-CNZ 데이터 시트보기 (PDF) - Cirrus Logic
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CS42L56-CNZ Datasheet PDF : 92 Pages
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CS42L56
4.11.2 Power-Down Sequence ....................................................................................................... 50
4.12 Recommended PGA to HP or Line Power Sequence (Analog Passthrough) .............................. 51
4.12.1 Power-Up Sequence ........................................................................................................... 51
4.12.2 Power-Down Sequence ....................................................................................................... 52
4.13 Control Port Operation .................................................................................................................. 53
4.13.1 SPI Control .......................................................................................................................... 53
4.13.2 I²C Control ........................................................................................................................... 53
4.13.3 Memory Address Pointer (MAP) .......................................................................................... 54
4.13.3.1 Map Increment (INCR) ............................................................................................. 54
5. REGISTER QUICK REFERENCE ........................................................................................................ 55
6. REGISTER DESCRIPTION .................................................................................................................. 57
6.1 Device I.D. Register (Address 01h) (Read Only) ............................................................................ 57
6.1.1 Device I.D. (Read Only) ........................................................................................................ 57
6.2 Device Revision Register (Address 02h) (Read Only) ................................................................... 57
6.2.1 Alpha Revision (Read Only) .................................................................................................. 57
6.2.2 Numeric Revision (Read Only) .............................................................................................. 57
6.3 Power Control 1 (Address 03h) ...................................................................................................... 57
6.3.1 Power Down VCM Bias Buffer .............................................................................................. 57
6.3.2 Power Down MIC Bias .......................................................................................................... 58
6.3.3 Power Down ADC Charge Pump .......................................................................................... 58
6.3.4 Power Down ADC x ............................................................................................................... 58
6.3.5 Power Down .......................................................................................................................... 58
6.4 Power Control 2 (Address 04h) ...................................................................................................... 58
6.4.1 Headphone Power Control .................................................................................................... 58
6.4.2 Line Power Control ................................................................................................................ 59
6.5 Clocking Control 1 (Address 05h) ................................................................................................... 59
6.5.1 Master/Slave Mode ............................................................................................................... 59
6.5.2 SCLK Polarity ........................................................................................................................ 59
6.5.3 SCLK Equals MCLK .............................................................................................................. 59
6.5.4 MCLK Pre-Divide ................................................................................................................... 59
6.5.5 MCLK Divide ......................................................................................................................... 60
6.5.6 MCLK Disable ....................................................................................................................... 60
6.6 Clocking Control 2 (Address 06h) ................................................................................................... 60
6.6.1 Clock Ratio Auto-Detect ........................................................................................................ 60
6.6.2 Clock Ratio ............................................................................................................................ 61
6.7 Serial Format (Address 07h) .......................................................................................................... 61
6.7.1 CODEC Digital Interface Format ........................................................................................... 61
6.8 Class H Control (Address 08h) ....................................................................................................... 62
6.8.1 Adaptive Power Adjustment .................................................................................................. 62
6.8.2 Charge Pump Frequency ...................................................................................................... 62
6.9 Misc. Control (Address 09h) ........................................................................................................... 62
6.9.1 Digital MUX ........................................................................................................................... 62
6.9.2 Analog Soft Ramp ................................................................................................................. 63
6.9.3 Analog Zero Cross ................................................................................................................ 63
6.9.4 Digital Soft Ramp .................................................................................................................. 63
6.9.5 Freeze Registers ................................................................................................................... 63
6.10 Status (Address 0Ah) (Read Only) ............................................................................................... 64
6.10.1 HPDETECT Pin Status (Read Only) ................................................................................... 64
6.10.2 Serial Port Clock Error (Read Only) .................................................................................... 64
6.10.3 DSP Engine Overflow (Read Only) ..................................................................................... 64
6.10.4 MIXx Overflow (Read Only) ................................................................................................. 64
6.10.5 ADCx Overflow (Read Only) ............................................................................................... 64
6.11 Playback Control (Address 0Bh) .................................................................................................. 65
6.11.1 Power Down DSP ................................................................................................................ 65
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DS851F2
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