AK7601 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
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AK7601 Datasheet PDF : 62 Pages
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[AK7601A]
FILTER CHARACTERISTICS
(Ta= -40 +85C; AVDD=4.5 5.5V, DVDD=3.0 5.5V)
Parameter
Symbol
min
typ
max
Unit
ADC Digital Filter (Decimation LPF):
Passband
(Note 13) 0.1dB
PB
0
-
17.3
kHz
0.2dB
-
18.3
-
kHz
3.0dB
-
21.1
-
kHz
Stopband
(Note 13)
SB
25.7
-
-
kHz
Passband Ripple
PR
-
-
0.04
dB
Stopband Attenuation
SA
68
-
-
dB
Group Delay Distortion
GD
-
0
-
s
Group Delay
(Note 14)
GD
-
16
-
1/fs
ADC Digital Filter (HPF):
Frequency Response (Note 13) 3dB
FR
-
0.86
-
Hz
0.1dB
-
5.9
-
Hz
DAC Digital Filter (LPF):
Passband
(Note 13) 0.06dB
PB
0
-
20.0
kHz
6.0dB
-
22.05
-
kHz
Stopband
(Note 13)
SB
24.1
-
-
kHz
Passband Ripple
PR
-
-
0.1
dB
Stopband Attenuation
SA
54
-
-
dB
Group Delay Distortion
GD
-
0
-
s
Group Delay
(Note 14)
GD
-
20
-
1/fs
DAC Digital Filter + Analog Filter:
Frequency Response (Note 15) 20~20kHz
FR
-
0.1
-
dB
Note 13. The passband and stopband frequencies scale with fs (system sampling rate). For example, when fs= 44.1kHz,
DAC is PB=0.45412*fs (@±0.06dB).
Note 14. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC. This time is from the set of 24bit data to
the input registers to the output of analog signal for DAC.
Note 15. The reference frequency of these responses is 1kHz.
SRC Digital Filter
Symbol
min
typ
max
Unit
Passband -0.01dB 0.985 ≤ FSO/FSI < 5.513
PB
0
0.4583FSI
kHz
0.656 ≤ FSO/FSI < 0.985
PB
0
0.4167FSI
kHz
0.492 ≤ FSO/FSI < 0.656
PB
0
0.2177FSI
kHz
0.459 ≤ FSO/FSI < 0.492
PB
0
0.1948FSI
kHz
Stopband
0.985 ≤ FSO/FSI < 5.513
SB
0.5417FSI
kHz
0.656 ≤ FSO/FSI < 0.985
SB
0.5021FSI
kHz
0.492 ≤ FSO/FSI < 0.656
SB
0.2813FSI
kHz
0.459 ≤ FSO/FSI < 0.492
SB
0.2604FSI
kHz
Passband Ripple
PR
0.01
dB
Stopband Attenuation 0.985 ≤ FSO/FSI < 5.513
SA
121.2
dB
0.656 ≤ FSO/FSI < 0.985
SA
121.4
dB
0.492 ≤ FSO/FSI < 0.656
SA
100.2
dB
0.459 ≤ FSO/FSI < 0.492
SA
103.3
dB
Group Delay (Ts=1/fs) (Note 16)
GD
64
Ts
Note 16.This delay is the period from the rising edge of ILRCK, just after the SDTI data is input, to the rising edge of
OLRCK, just after the SDTO data is output, when there is no phase difference between ILRCK and OLRCK.
MS1446-E-01
-9-
2015/05
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