RT8120 데이터 시트보기 (PDF) - Richtek Technology

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RT8120

Single-Phase Synchronous Buck PWM Controller

Richtek Technology 

RT8120

80 80

60

fP1

40 40

20

Loop Gain

fLC

fZ1

Compensation

Gain

fP2

00

Modulator

-20 Gain

fESR

-40-40

-60-60

110H0zvdb(vo) vdb(comp2)11000vHd0zb(lo)

11.0kKHz

110K0Hzk

FrequFreequnenccyy (Hz)

11000K0Hzk

1.01MHzM

Figure 6. Typical Bode Plot of a Voltage Mode Buck

Converter

The DC gain of the modulator is the input voltage (VIN)

divided by the peak-to-peak oscillator voltage VOSC.

GainMODULATOR

=

VIN

ΔVOSC

The output LC filter introduces a double pole, 40dB/decade

gain slope above its corner resonant frequency, and a total

phase lag of 180 degrees. The resonant frequency of the

LC filter is expressed as :

fLC = 2π

1

LOUT x COUT

The ESR zero is contributed by the ESR associated with

the output capacitance. Note that this requires that the

output capacitor should have enough ESR to satisfy

stability requirements. The ESR zero of the output

capacitor is expressed as follows :

fESR

=

2π

1

x COUT

x ESR

The goal of the compensation network is to provide

adequate phase margin (usually greater than 45 degrees)

and the highest bandwidth (0dB crossing frequency). It is

also recommended to manipulate loop frequency response

that its gain crosses over 0dB at a slope of −20dB/dec.

According to Figure 6, the compensation network

frequency is as below :

fP1 = 0

fP2

=

2π

x RC

1

x

⎛ CC

⎜

⎝

CC

x Cp ⎞

+

CP

⎟

⎠

fZ1

=

2π

1

x RC

x CC

To determine the 0dB crossing frequency (fC, control loop

bandwidth) is the first step of compensator design. Usually,

the fC is set to 0.1 to 0.3 times the switching frequency.

The second step is to calculate the open loop modulator

gain and find out the gain loss at fC. The third step is to

design a compensator gain that can compensate the

modulator gain loss at fC. The final step is to design fZ1

and fP2 to allow the loop sufficient phase margin. fZ1 is

designed to cancel one of the double poles of modulator.

Usually, place fZ1 before fLC. fP2 is usually placed below

the switching frequency (typically, 0.5 to 1 times the

switching frequency) to cancel high frequency noise.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX) − TA ) / θJA

Where TJ(MAX) is the maximum junction temperature, TA

is the ambient temperature, and θJA is the junction to

ambient thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θJA, is layout dependent. For

SOP-8 package, the thermal resistance, θJA, is 188°C/W

on a standard JEDEC 51-7 four-layer thermal test board.

For SOP-8 (Exposed Pad) package, the thermal

resistance, θJA, is 30.6°C/W on a standard JEDEC 51-7

four-layer thermal test board. The maximum power

dissipation at TA = 25°C can be calculated by the following

formulas :

PD(MAX) = (125°C − 25°C ) / (188°C/W) = 0.53W for

SOP-8 package

PD(MAX) = (125°C − 25°C ) / (30.6°C/W) = 3.26W for

SOP-8 (Exposed Pad) package

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is a registered trademark of Richtek Technology Corporation.

DS8120-08 September 2013

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