IT7001M 데이터 시트보기 (PDF) - ITE Tech. INC.

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IT7001M

Programmable 8-Bit Binary Counter with Synchronous Preset Enable

ITE Tech. INC. 

IT7001M/IT7001N Pin Description

5. IT7001M/IT7001N Pin Description

Signal

VCC

GND

J0 to J7

CLK, CLK_N

Pin(s) No.

16

8

1-7,9

14,15

SPE_N

11

PR_N

12

CLR_N

10

Q

13

Attribute





I

I

I

I

I

O

Description

Power

Ground

Count data input for option

Clock inputs CLK: Rising edge trigger

CLK_N: Falling edge trigger

Preset input for Jn data

Please refer to the table below

Preset input for D-type Flip Flop (Initialize “L” at Q output)

Please refer to the table below

Clear input for D-type Flip Flop (Initialize “H” at Q output)

Please refer to the table below

Output for D-type Flip Flop

Table 5-1. Function Table of CLR_N, PR_N and SPE_N Pins

Control Inputs

CLR_N PR_N SPE_N

Mode

Operation Description

H

H

H Generally count

Down count at the rising edge of clock (CLK)

Down count at the falling edge of clock (CLK_N)

X

X

L

Synchronous preset Jn data is preset at the rise of clock (CLK) ,

the fall of clock (CLK_N)

L

H

 Initialize of Q output Initialize of Q = “L”

H

L

 Initialize of Q output Initialize of Q = “H”

H: High level

X: Immaterial

L: Low level

: Irrespective of condition

1) Synchronous preset (SPE_N) input can set max 256 down counts.

2) When the count value is 0, the next clock pulse presets the data to invert the output.

3) CLR_N and PR_N inputs initialize the output data.

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IT7001M/IT7001N V0.2

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