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NT5CB128M8DN

1Gb DDR3 D-die SDRAM

Nanya Technology 

NT5CB128M8DN/NT5CB64M16DP

NT5CC128M8DN/NT5CC64M16DP

1Gb DDR3 D-die SDRAM

Data Setup, Hold, and Slew Rate De-rating

For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDH(base)

and tDH(base) value to the delta tDS and delta tDH derating value respectively.

Example: tDS (total setup time) = tDS(base) + delta tDS

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the

first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line

between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the

nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the tangent line to the actual signal

from the ac level to dc level is used for derating value.

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the

first crossing of Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line

between shaded ‘dc level to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the

nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to the actual signal

from the dc level to Vref(dc) level is used for derating value.

For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)

at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).

For slew rates in between the values listed in the following tables, the derating values may be obtained by linear

interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

Table 70: Data Setup and Hold Base-Values

Unit [ps] reference DDR3-1066

DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Units

tDS(base)AC175 VIH/L(ac)

25

-

-

tDS(base)AC150 VIH/L(ac)

75

30

10

tDS(base)AC135 VIH/L(ac)

-

-

-

tDH(base)DC100 VIH/L(dc)

100

65

45

1.35V

tDS(base)AC160 VIH/L(ac)

40

-

-

tDS(base)AC135 VIH/L(ac)

90

45

25

tDH(base)DC90 VIH/L(dc)

110

75

55

Note: ac/dc referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate

-

-

TBD

TBD

-

-

TBD

-

ps

-

ps

TBD

ps

TBD

ps

-

ps

-

ps

TBD

ps

REV 1.2

May. 2011

CONSUMER DRAM

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All rights reserved

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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