NT5CB128M8DN 데이터 시트보기 (PDF) - Nanya Technology

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NT5CB128M8DN

1Gb DDR3 D-die SDRAM

Nanya Technology 

NT5CB128M8DN/NT5CB64M16DP

NT5CC128M8DN/NT5CC64M16DP

1Gb DDR3 D-die SDRAM

Fig. 4: Reset and Initialization Sequence at Power- on Ramping (Cont’d)

Reset Procedure at Stable Power (Cont’d)

The following sequence is required for RESET at no power interruption initialization.

1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be

maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns).

2. Follow Power-up Initialization Sequence step 2 to 11.

3. The Reset sequence is now completed. DDR3/L SDRAM is ready for normal operation.

Fig. 5: Reset Procedure at Power Stable Condition

REV 1.2

May. 2011

CONSUMER DRAM

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