BD82HM55QMNT 데이터 시트보기 (PDF) - Intel

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BD82HM55QMNT

Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel 

12.1.24MCTL—Message Control Register

(Gigabit LAN—D25:F0) .......................................................................... 451

12.1.25MADDL—Message Address Low Register

(Gigabit LAN—D25:F0) .......................................................................... 452

12.1.26MADDH—Message Address High Register

(Gigabit LAN—D25:F0) .......................................................................... 452

12.1.27MDAT—Message Data Register

(Gigabit LAN—D25:F0) .......................................................................... 452

12.1.28FLRCAP—Function Level Reset Capability

(Gigabit LAN—D25:F0) .......................................................................... 452

12.1.29FLRCLV—Function Level Reset Capability Length and Version

(Gigabit LAN—D25:F0) .......................................................................... 453

12.1.30DEVCTRL—Device Control (Gigabit LAN—D25:F0) ..................................... 453

13 LPC Interface Bridge Registers (D31:F0) ............................................................... 455

13.1 PCI Configuration Registers (LPC I/F—D31:F0) .................................................... 455

13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) .............................. 456

13.1.2 DID—Device Identification Register (LPC I/F—D31:F0)............................... 456

13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)................................. 457

13.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)........................................ 457

13.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............................ 458

13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ............................. 458

13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) ..................................... 459

13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0) .................................... 459

13.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) ............................ 459

13.1.10HEADTYP—Header Type Register (LPC I/F—D31:F0) .................................. 459

13.1.11SS—Sub System Identifiers Register (LPC I/F—D31:F0) ............................. 460

13.1.12PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)........................... 460

13.1.13ACPI_CNTL—ACPI Control Register (LPC I/F—D31:F0) ............................... 461

13.1.14GPIOBASE—GPIO Base Address Register (LPC I/F—D31:F0) ....................... 461

13.1.15GC—GPIO Control Register (LPC I/F—D31:F0) .......................................... 462

13.1.16PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) ................................................................................ 463

13.1.17SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0) ................................................................................ 464

13.1.18PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0) ................................................................................ 465

13.1.19LPC_IBDF—IOxAPIC Bus:Device:Function

(LPC I/F—D31:F0) ................................................................................ 465

13.1.20LPC_HnBDF – HPET n Bus:Device:Function

(LPC I/F—D31:F0) ................................................................................ 466

13.1.21LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0) ................................................................................ 467

13.1.22LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ................................ 468

13.1.23GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0) ................................................................................ 469

13.1.24GEN2_DEC—LPC I/F Generic Decode Range 2 Register

(LPC I/F—D31:F0) ................................................................................ 469

13.1.25GEN3_DEC—LPC I/F Generic Decode Range 3 Register

(LPC I/F—D31:F0) ................................................................................ 470

13.1.26GEN4_DEC—LPC I/F Generic Decode Range 4 Register

(LPC I/F—D31:F0) ................................................................................ 470

13.1.27ULKMC—USB Legacy Keyboard / Mouse Control

(LPC I/F—D31:F0) ................................................................................ 471

13.1.28LGMR—LPC I/F Generic Memory Range

(LPC I/F—D31:F0) ................................................................................ 472

13.1.29FWH_SEL1—Firmware Hub Select 1 Register

(LPC I/F—D31:F0) ................................................................................ 473

13.1.30FWH_SEL2—Firmware Hub Select 2 Register

(LPC I/F—D31:F0) ................................................................................ 474

13.1.31FWH_DEC_EN1—Firmware Hub Decode Enable

Register (LPC I/F—D31:F0) .................................................................... 475

13.1.32BIOS_CNTL—BIOS Control Register

(LPC I/F—D31:F0) ................................................................................ 477

13.1.33FDCAP—Feature Detection Capability ID

(LPC I/F—D31:F0) ................................................................................ 478

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