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STM8AP6268TA 데이터 시트보기 (PDF) - STMicroelectronics

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STM8AP6268TA Datasheet PDF : 89 Pages
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STM8AF61xx, STM8AF62xx
Product overview
5.9.1
5.9.2
Serial peripheral interface (SPI)
The devices covered by this datasheet contain one SPI. The SPI is available on all the
supported packages.
Maximum speed: 10 Mbit/s or fMASTER/2 both for master and slave
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave mode/master mode management by hardware or software for both master and
slave
Programmable clock polarity and phase
Programmable data order with MSB-first or LSB-first shifting
Dedicated transmission and reception flags with interrupt capability
SPI bus busy status flag
Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– CRC error checking for last received byte
Inter integrated circuit (I2C) interface
The devices covered by this datasheet contain one I2C interface. The interface is available
on all the supported packages.
I2C master features:
– Clock generation
– Start and stop generation
I2C slave features:
– Programmable I2C address detection
– Stop bit detection
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
– Standard speed (up to 100 kHz),
– Fast speed (up to 400 kHz)
Status flags:
– Transmitter/receiver mode flag
– End-of-byte transmission flag
– I2C busy flag
Error flags:
– Arbitration lost condition for master mode
– Acknowledgement failure after address/data transmission
– Detection of misplaced start or stop condition
– Overrun/underrun if clock stretching is disabled
Doc ID 14952 Rev 6
21/89

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