HD404668 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HD404668

Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit

Hitachi -> Renesas Electronics 

HD404669 Series

Bits in the interrupt control bits area and register flag area can be set and reset by the

SEM or SEMD instruction and the REM or REMD instruction, and tested by the TM or

TMD instruction. They are not affected by any other instructions.

The following restrictions apply to individual bits.

SEM/SEMD

REM/REMD

TM/TMD

IE

IM

LSON

IF

ICSF

ICEF

RAME

RSP

WDON

DTON

Allowed

Allowed

Not executed

Allowed

Not executed

Allowed

Not executed in active mode

Used in subactive mode

Allowed

Not executed

Allowed

Allowed

Allowed

Inhibited

Inhibited

Allowed

Not used

Not executed

Not executed

Inhibited

Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.

DTON is always reset in active mode.

If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,

the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

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