ADCMP602 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

ADCMP602

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators

Analog Devices 

ADCMP600/ADCMP601/ADCMP602

Leaving the LE/HYS pin disconnected results in a fixed

hysteresis of 2 mV; driving this pin high removes hysteresis. The

maximum hysteresis that can be applied using this pin is

approximately 160 mV. Figure 21 illustrates the amount of

hysteresis applied as a function of the external resistor value,

and Figure 11 illustrates hysteresis as a function of the current.

The hysteresis control pin appears as a 1.25 V bias voltage seen

through a series resistance of 7 kΩ. The bias voltage changes

± 20% throughout the hysteresis control range. The advantages

of applying hysteresis in this manner are improved accuracy,

improved stability, reduced component count, and maximum

versatility. An external bypass capacitor is not recommended on

the HYS pin because it impairs the latch function and often

degrades the jitter performance of the device. As described in the

Using/Disabling the Latch Feature section, hysteresis control

need not compromise the latch function.

CROSSOVER BIAS POINT

In both op amps and comparators, rail-to-rail inputs of this type

have a dual front-end design. Certain devices are active near the

VCC rail and others are active near the GND rail. At some predeter-

mined point in the common-mode range, a crossover occurs. At

this point, normally VCC/2, the direction of the bias current reverses

and the measured offset voltages and currents change.

The ADCMP600/ADCMP601/ADCMP602 comparators

slightly elaborate on this scheme. Crossover points can be found

at approximately 0.8 V and 1.6 V.

250

200

VCC = 5.5V

150

100

50

VCC = 2.5V

0

50

150

250

350

450

550

650

HYSTERESIS RESISTOR (kΩ)

Figure 21. Hysteresis vs. RHYS Control Resistor

MINIMUM INPUT SLEW RATE REQUIREMENT

With the rated load capacitance and normal good PC Board

design practice, as discussed in the Optimizing Performance

section, these comparators should be stable at any input slew

rate with no hysteresis. Broadband noise from the input stage is

observed in place of the violent chattering seen with most other

high speed comparators. With additional capacitive loading or

poor bypassing, oscillation is observed. This oscillation is due to

the high gain bandwidth of the comparator in combination with

feedback parasitics in the package and PC board. In many

applications, chattering is not harmful.

Rev. A | Page 12 of 16

Share Link: