LTC6803-1 데이터 시트보기 (PDF) - Linear Technology

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LTC6803-1

Multicell Battery Stack Monitor

Linear Technology 

LTC6803-1/LTC6803-3

OPERATION

Data Link Layer

Clock Phase And Polarity: The LTC6803 SPI compatible

interface is configured to operate in a system using CPHA

= 1 and CPOL = 1. Consequently, data on SDI must be

stable during the rising edge of SCKI.

Data Transfers: Every byte consists of 8 bits. Bytes are

transferred with the most significant bit (MSB) first. On a

write, the data value on SDI is latched into the device on

the rising edge of SCKI (Figure 3). Similarly, on a read, the

data value output on SDO is valid during the rising edge of

SCKI and transitions on the falling edge of SCKI (Figure 4).

CSBI must remain low for the entire duration of a com-

mand sequence, including between a command byte and

subsequent data. On a write command, data is latched in

on the rising edge of CSBI.

Network Layer

PEC Byte: The packet error code (PEC) byte is a cyclic

redundancy check (CRC) value calculated for all of the

bits in a register group in the order they are passed, using

the initial PEC value of 01000001 (0x41) and the following

characteristic polynomial:

x8 + x2 + x + 1

To calculate the 8-bit PEC value, a simple procedure can

be established:

1. Initialize the PEC to 0100 0001.

2. For each bit DIN coming into the register group, set

IN0 = DIN XOR PEC[7], then IN1=PEC[0] XOR IN0,

IN2 = PEC[1] XOR IN0.

3. Update the 8-bit PEC as PEC[7] = PEC[6],

PEC[6] = PEC[5],……PEC[3] = PEC[2], PEC[2] = IN2,

PEC[1] = IN1, PEC[0] = IN0.

4. Go back to step 2 until all data are shifted. The 8-bit

result is the final PEC byte.

CSBI

SCKI

SDI

MSB (CMD) BIT 6 (CMD)

LSB (PEC) MSB (DATA)

LSB (PEC)

680313 F03

Figure 3. Transmission Format (Write)

CSBI

SCKI

SDI

MSB (CMD) BIT 6 (CMD)

LSB (PEC)

SDO

MSB (DATA)

LSB (PEC)

680313 F04

Figure 4. Transmission Format (Read)

680313f

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