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ISL12022M

Real Time Clock with Embedded Crystal, ±5ppm Accuracy

Intersil 

ISL12022M

BIT

ALARM

REGISTER 7 6 5 4 3 2 1 0 HEX

DESCRIPTION

SCA0

1 0 1 1 0 0 0 0 B0h Seconds set to 30,

enabled

MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled

HRA0 0 0 0 0 0 0 0 0 00h Hours disabled

Time Stamp Battery to VDD Registers (TSB2V)

The Time Stamp Battery to VDD Register bytes are identical to

the RTC register bytes, except they do not extend beyond

Month. The Time Stamp captures the LAST transition of VBAT

to VDD (only the last event of a series of power-up/power-down

events is retained). Set CLRTS = 1 to clear this register (Add

09h, PWR_VDD register).

DTA0

MOA0

DWA0

0 0 0 0 0 0 0 0 00h Date disabled

0 0 0 0 0 0 0 0 00h Month disabled

0 0 0 0 0 0 0 0 00h Day of week disabled

Once the registers are set, the following waveform will be

seen at IRQ/FOUT:

RTC AND ALARM REGISTERS ARE BOTH “30s”

DST Control Registers (DSTCR)

8 bytes of control registers have been assigned for the

Daylight Savings Time (DST) functions. DST beginning (set

Forward) time is controlled by the registers DstMoFd,

DstDwFd, DstDtFd, and DstHrFd. DST ending time (set

Backward or Reverse) is controlled by DstMoRv, DstDwRv,

DstDtRv and DstHrRv.

Tables 20 and 21 describe the structure and functions of the

DSTCR.

DST FORWARD REGISTERS (20H TO 23H)

60s

DST forward is controlled by the following DST Registers:

FIGURE 14. IRQ/FOUT WAVEFORM

Note that the status register ALM bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

Time Stamp VDD to Battery Registers (TSV2B)

The TSV2B Register bytes are identical to the RTC register

bytes, except they do not extend beyond the Month. The Time

Stamp captures the FIRST VDD to Battery Voltage transition

time, and will not update upon subsequent events until cleared

(only the first event is captured before clearing). Set CLRTS = 1

to clear this register (Add 09h, PWR_VDD register).

Note that the time stamp registers are cleared to all “0”,

including the month and day, which is different from the RTC

and alarm registers (those registers default to 01h). This is

the indicator that no time stamping has occurred since the

last clear or initial power-up. Once a time stamp occurs,

there will be a non-zero time stamp.

DST Enable

DSTE is the DST Enabling Bit located in bit 7 of register 20h

(DstMoFdxx). Set DSTE = 1 will enable the DSTE function.

Upon powering up for the first time (including battery), the

DSTE bit defaults to “0”. When DSTE is set to “1” the RTC

time must be at least one hour before the scheduled DST

time change for the correction to take place. When DSTE is

set to “0”, the DSTADJ bit in the Status Register

automatically resets to “0”.

DST Month Forward

DstMoFd sets the Month that DST starts. The format is the

same as for the RTC register month, from 1 to 12. The

default value for the DST begin month is 00h.

TABLE 20. DST FORWARD REGISTERS

ADDRESS FUNCTION

7

6

5

4

3

2

1

0

20h

Month Forward DSTE

0

0

MoFd20

MoFd13

MoFd12

MoFd11 MoFd10

21h

Day Forward

0

DwFdE

WkFd12

WkFd11

WkFd10

DwFd12

DwFd11 DwFd10

22h

Date Forward

0

0

DtFd21

DtFd20

DtFd13

DtFd12

DtFd11

DtFd10

23h

Hour Forward

0

0

HrFd21

HrFd20

HrFd13

HrFd12

HrFd11

HrFd10

ADDRESS

NAME

7

24h

Month Reverse

0

25h

Day Reverse

0

26h

Date Reverse

0

27h

Hour Reverse

0

TABLE 21. DST REVERSE REGISTERS

6

5

4

3

0

0

MoRv20 MoRv13

DwRvE

WkRv12 WkRv11 WkRv10

0

DtRv21

DtRv20

DtRv13

0

HrRv21

HrRv20

HrRv13

2

MoRv12

DwRv12

DtRv12

HrRv12

1

MoRv11

DwRv11

DtRv11

HrRv11

0

MoRv10

DwRv10

DtRv10

HrRv10

20

FN6668.5

July 10, 2009

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