ALC202 데이터 시트보기 (PDF) - Realtek Semiconductor
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ALC202 Datasheet PDF : 42 Pages
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7.2.3 AC-Link Clocks
Parameter
Symbol
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
Tclk_period
BIT_CLK high pulse width (note 2)
BIT_CLK low pulse width (note 2)
Tclk_high
Tclk_low
SYNC frequency
SYNC period
Tsync_period
SYNC high pulse width
Tsync_high
SYNC low pulse width
Tsync_low
Note 1: Worse case duty cycle restricted to 45/55.
Minimum
-
-
-
36
36
-
-
-
-
Typical
12.288
81.4
-
40.7
40.7
48.0
20.8
1.3
19.5
ALC202/ALC202A
Maximum
-
-
750
45
45
-
-
-
-
Units
MHz
ns
ps
ns
ns
KHz
µs
µs
µs
BIT_CLK and SYNC timing diagram
7.2.4 Data Output and Input Timing
Parameter
Symbol
Minimum
Typical
Maximum
Output Valid Delay from rising
tco
-
edge of BIT_CLK
-
15
Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
Note 2: 50pF external load
Parameter
Symbol
Minimum
Typical
Maximum
Input Setup to falling edge of
tsetup
10
-
-
BIT_CLK
Input Hold from falling edge of
thold
10
-
-
BIT_CLK
Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
Parameter
Symbol
Minimum
Typical
Maximum
BIT_CLK combined rise or fall
-
-
7
plus flight time
SDATA combined rise or fall plus
-
-
7
flight time
Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes.
Units
ns
Units
ns
ns
Units
ns
ns
2002/07/30
Data Output and Input timing diagram
27
Rev.1.28
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