LM25115SD 데이터 시트보기 (PDF) - National ->Texas Instruments

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LM25115SD

Secondary Side Post Regulator Controller

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Gate Drivers Outputs (HO & LO)

(Continued)

mize voltage transients due to parasitic inductances and the

high peak output currents of the drivers. The recommended

range of the HB capacitor is 0.047µF to 0.22µF.

Both drivers are controlled by the PWM logic signal from the

PWM latch. When the phase signal is low, the outputs are

held in the reset state with the low-side MOSFET on and the

high-side MOSFET off. When the phase signal switches to

the high state, the PWM latch reset signal is de-asserted.

The high-side MOSFET remains off until the PWM latch is

set by the PWM comparator (CRMIX > CV as shown in

Figure 4). When the PWM latch is set, the LO driver turns off

the low-side MOSFET and the HO driver turns on the high-

side MOSFET. The high-side pulse is terminated when the

phase signal falls and the SYNC input comparator resets the

PWM latch.

Free-Run Mode

The LM25115 can be operated as a conventional synchro-

nous buck controller with a dc input supply instead of the

square wave phase signal. In the dc or free-run mode, the

LM25115 PWM controller synchronizes to an internal clock

signal instead of the phase signal pulses. The clock fre-

quency in the free-run mode is programmed by the SYNC

pin resistor and RAMP pin capacitor. Connecting a resistor

between a dc bias supply and the SYNC pin produces a

current ISYNC which controls the charging current of the

RAMP pin capacitor . The RAMP capacitor is charged until

its voltage reaches the free-run mode peak threshold of

2.25V. The RAMP capacitor is then discharged for 300ns

before beginning a new PWM cycle. The 300ns reset time of

the RAMP pin sets the minimum off time of the PWM con-

troller in the free-run mode. The internal clock frequency in

the free-run mode is set by the synchronization current,

ramp capacitor, free-run peak threshold, and 300ns dead-

time.

FCLK ) 1 / ((CRAMP x 2.25V) / (ISYNC x 3) + 300ns)

Note that the VCC supply can be used as the dc bias to

produce ISYNC. Note that the input voltage feedforward is no

longer functional in this operating mode, so the loop gain will

vary as a function of Vin. The LM25115 controls the buck

power stage with leading edge pulse width modulaton to

hold off the high-side driver until the necessary volt*seconds

is established for regulation. Other features described for the

secondary side post regulator apply in the free run mode

operation. They include voltage mode control with current

injection, positive and negative current limit, programmable

soft-start, adaptive delays for outputs, and thermal protec-

tion.

Thermal Protection

Internal thermal shutdown circuitry is provided to protect the

integrated circuit in the event the maximum junction tem-

perature limit is exceeded. When activated, typically at 165

degrees Celsius, the controller is forced into a low power

standby state with the output drivers and the bias regulator

disabled. The device will restart when the junction tempera-

ture falls below the thermal shutdown hysteresis, which is

typically 25 degrees. The thermal protection feature is pro-

vided to prevent catastrophic failures from accidental device

overheating.

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