MAX7418 데이터 시트보기 (PDF) - Maxim Integrated
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MAX7418 Datasheet PDF : 14 Pages
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5th-Order, Lowpass,
Switched-Capacitor Filters
VSUPPLY
2V/div
A
2V/div
B
2V/div
C
200µs/div
A: 1kHz INPUT SIGNAL
B: MAX7419 BESSEL FILTER RESPONSE; fC = 5kHz
C: MAX7420 BUTTERWORTH FILTER RESPONSE; fC = 5kHz
Figure 3. Bessel vs. Butterworth Filter Response
Internal Clock
When using the internal oscillator, the capacitance
(COSC) on CLK determines the oscillator frequency:
fOSC(kHz) =
k
COSC (pF)
where
k = 87 x 103 for the
MAX7418/MAX7421/MAX7422/MAX7425
and
k = 110 x 103 for the
MAX7419/MAX7420/MAX7423/ MAX7424.
Since COSC is in the low picofarads, minimize the stray
capacitance at CLK so that it does not affect the inter-
nal oscillator frequency. Varying the rate of the internal
oscillator adjusts the filter’s corner frequency by a
100:1 clock-to-corner frequency ratio. For example, an
internal oscillator frequency of 2.2MHz produces a
nominal corner frequency of 2.2kHz.
Input Impedance vs. Clock Frequencies
The MAX7418–MAX7425s’ input impedance is effective
as a switched-capacitor resistor and is inversely propor-
tional to frequency. The input impedance values deter-
mined by the equation represents the average input
impedance, since the input current is not continuous.
As a rule, use a driver with an output resistance less
than 10% of the filter’s input impedance.
Estimate the input impedance of the filter by using the
following formula:
0.1µF
INPUT
CLOCK
VDD
SHDN
OUT
OUTPUT
IN
COM
0.1µF
50k
MAX7418–
MAX7425
CLK
OS
50k
0.1µF
50k
GND
Figure 4. Offset Adjustment Circuit
ZIN
=
1
(fCLK × CIN)
where fCLK = clock frequency and CIN = 1pF.
Low-Power Shutdown Mode
The MAX7418–MAX7425 have a shutdown mode that is
activated by driving SHDN low. In shutdown mode, the
filter supply current reduces to 0.2µA, and the output of
the filter becomes high impedance. For normal opera-
tion, drive SHDN high or connect to VDD.
Applications Information
Offset (OS) and Common-Mode (COM)
Input Adjustment
COM sets the common-mode input voltage and is
biased at midsupply with an internal resistor-divider. If
the application does not require offset adjustment, con-
nect OS to COM. For applications in which offset
adjustment is required, apply an external bias voltage
through a resistor-divider network to OS, as shown in
Figure 4. For applications that require DC level shifting,
adjust OS with respect to COM. (Note: Do not leave OS
unconnected.) The output voltage is represented by
these equations:
VOUT = (VIN − VCOM) + VOS
VCOM
=
VDD
2
(typ)
where (VIN - VCOM) is lowpass filtered by the SCF and
OS is added at the output stage. See the Electrical
Characteristics table for the input voltage range of COM
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