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AD745JN 데이터 시트보기 (PDF) - Analog Devices
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AD745JN
Ultralow Noise, High Speed, BiFET Op Amp
Analog Devices
AD745JN Datasheet PDF : 12 Pages
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11
12
AD745
C
B
= C
S
R
B
= R
S
FOR
R
S
>> R
1
OR R
2
R
2
R
1
C
B
R
B
OUTPUT
AD745
C
S
R
S
NONINVERTING
CONNECTION
C
B
= C
F
II
C
S
R
B
= R
1
II
R
S
C
S
R
S
C
B
C
F
R
1
AD745
OUTPUT
R
B
INVERTING
CONNECTION
Figure 40. Optional External Components for Balancing Source Impedances
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic Mini-DIP (N) Package
8
0.31
(7.87)
1
5
0.25
(6.35)
4
0.165
+-
0.01
(4.19
+-
0.25)
SEATING
PLANE
0.125 (3.18)
MIN
0.39 (9.91)
MAX
0.035
+-
0.01
(0.89 +- 0.25)
0.30 (7.62)
REF
0.011 +- 0.003
(0.28 +- 0.08)
O.018 +- 0.003
(0.46 +- 0.08)
0.100
(2.54)
TYP
0.18 +- 0.03
0 - 15
(4.57
+-
0.76)
8-Pin Cerdip (Q) Package
0.005 (0.13) MIN 0.055 (1.35) MAX
8
5
0.320 (8.13)
0.290 (7.37)
1
4
0.405 (10.29) MAX
0.070 (1.78)
0.030 (0.76)
0.200
(5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.310 (7.87)
0.220 (5.59)
0.015 (0.38)
0.008 (0.20)
0.023 (0.58)
0.014 (0.36)
0.100 (2.54)
0 - 15
BSC
SEATING PLANE
16-Pin SOIC (R) Package
16
0.419 (10.64)
0.394 (10.01)
1
9
0.292 (7.42)
0.300 (7.62)
8
0.104 (2.64)
0.003 (2.36)
0.413 (10.49)
0.396 (10.11)
0.011 (0.279)
0.004 (0.102)
0 -8
0.0500 (1.27)
0.0157 (0.40)
0.0291 (0.74)
x 45
0.0098 (0.25)
SEATING
PLANE
0.060
(1.27)
REF
0.019 (0.483)
0.014 (0.356)
0.0125 (0.32)
0.0091 (0.23)
SEE
DETAIL
ABOVE
–12–
REV. C
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