MBM29LV800BA-120PFTR 데이터 시트보기 (PDF) - Fujitsu

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MBM29LV800BA-120PFTR

CMOS 8M (1M × 8/512K × 16) BIT

Fujitsu 

MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12

Mode

Program

Erase

Erase-Suspend Read

(Erase-Suspended Sector)

(Note 1)

Erase-Suspend Program

DQ7

DQ6

DQ2

DQ7

Toggle

1

0

Toggle

Toggle

1

1

Toggle

DQ7

Toggle (Note 1)

1 (Note 2)

Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate

logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to

toggle.

RY/BY

Ready/Busy

The MBM29LV800TA/BA provide a RY/BY open-drain output pin as a way to indicate to the host system that the

Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy

with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or

erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase

commands. If the MBM29LV800TA/BA are placed in an Erase Suspend mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a

busy condition during the RESET pulse. Refer to Figure 11 and 12 for a detailed timing diagram. The RY/BY

pin is pulled high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV800TA/BA devices. When

this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0

to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin

becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer

to Figures 13, 14 and 15 for the timing diagram.

Data Protection

The MBM29LV800TA/BA are designed to offer protection against accidental erasure or programming caused by

spurious system level signals that may exist during power transitions. During power up the devices automatically

reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the

memory contents only occurs after successful completion of specific multi-bus cycle command sequences.

The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up

and power-down transitions or system noise.

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