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AD9814

Complete 14-Bit CCD/CIS Signal Processor

Analog Devices 

AD9814

APPLICATIONS INFORMATION

Circuit and Layout Recommendations

The recommended circuit configuration for 3-Channel CDS

mode operation is shown in Figure 15. The recommended input

coupling capacitor value is 0.1 µF (see Circuit Operation section

for more details). A single ground plane is recommended for the

AD9814. A separate power supply may be used for DRVDD,

the digital driver supply, but this supply pin should still be

decoupled to the same ground plane as the rest of the AD9814.

The loading of the digital outputs should be minimized, either

by using short traces to the digital ASIC, or by using external

digital buffers. To minimize the effect of digital transients during

major output code transitions, the falling edge of CDSCLK2

should occur coincident with or before the rising edge of

ADCCLK (see Figures 1 through 4 for timing). All 0.1 µF

decoupling capacitors should be located as close as possible to

the AD9814 pins. When operating in single channel mode, the

unused analog inputs should be grounded.

Figure 16 shows the recommended circuit configuration for 3-

Channel SHA mode. All of the above considerations also apply

for this configuration, except that the analog input signals are

directly connected to the AD9814 without the use of coupling

capacitors. The analog input signals must already be dc-biased

between 0 V and 4 V (see the Circuit Operation section for

more details).

CLOCK INPUTS 3

+5V/3V

0.1␮F

8

DATA OUTPUTS

+5V

1 CDSCLK1

AVDD 28

2 CDSCLK2

AVSS 27

3 ADCCLK

VINR 26

4 OEB

OFFSET 25

5 DRVDD

AD9814

VING 24

6 DRVSS

CML 23

7 D7 (MSB)

VINB 22

8 D6

CAPT 21

9 D5

CAPB 20

10 D4

AVSS 19

11 D3

AVDD 18

12 D2

SLOAD 17

13 D1

SCLK 16

14 D0 (LSB)

SDATA 15

0.1␮F

3

0.1␮F

0.1␮F

0.1␮F

RED INPUT

GREEN INPUT

BLUE INPUT

0.1␮F

0.1␮F

1.0␮F

0.1␮F

+

0.1␮F

10␮F 0.1␮F

0.1␮F

+5V

SERIAL INTERFACE

Figure 15. Recommended Circuit Configuration, 3-Channel CDS Mode

CLOCK INPUTS 3

+5V/3V

0.1␮F

8

DATA OUTPUTS

+5V

RED INPUT

1 CDSCLK1

AVDD 28

2 CDSCLK2

AVSS 27

3 ADCCLK

VINR 26

4 OEB

OFFSET 25

5 DRVDD

AD9814

VING 24

6 DRVSS

CML 23

7 D7 (MSB)

VINB 22

8 D6

CAPT 21

9 D5

CAPB 20

10 D4

AVSS 19

11 D3

AVDD 18

12 D2

SLOAD 17

13 D1

SCLK 16

14 D0 (LSB)

SDATA 15

0.1␮F

GREEN INPUT

BLUE INPUT

0.1␮F

0.1␮F

+

0.1␮F

10␮F 0.1␮F

0.1␮F

+5V

3

SERIAL INTERFACE

Figure 16. Recommended Circuit Configuration, 3-Channel SHA Mode

(Analog Inputs Sampled with Respect to Ground)

–14–

REV. 0

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