5504-CGT 데이터 시트보기 (PDF) - TDK Corporation

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5504-CGT

Direct Conversion Receiver

TDK Corporation 

5504 DCR

Direct Conversion Receiver

FUNCTIONAL DESCRIPTION

AGC Amplifier

The 5504 RF input can be driven differentially or

single ended. The RFp and RFn inputs are self-

biasing and are designed to be driven from a 50

Ohm source. For single-ended operation, the RFn

pin should be AC coupled to analog ground. A gain

control input, AGC, provides a 25 dB gain variation

with 0V providing minimum gain and 4V providing

maximum gain.

I/Q Mixer

The AGC amplifier drives the RF port of two identical

double balanced mixers. The LO ports of these

mixers are driven from an on-chip quadrature

network.

Low Pass Filtering and Buffering

Following each mixer, a buffer amplifier is provided

for driving an external passive low-pass filter. The

nominal output impedance for IO1 and Q01 is 50

ohms. A second high impedance buffer amplifier is

provided (IIN or QIN) for additional gain and isolation

after the filter. The figure below shows a typical filter

designed for 20 Megasymbol per second operation:

IO1/QO1

12pF

470nH

68pF

680nH

68pF

0.1 F

IIN/QIN

Dual VCO

The 5504 uses two VCOs to cover the entire

specified tuning range. Both VCOs use nearly

identical architecture with the only difference being

slight design modifications to optimize the range of

operation. The lower range VCO requires an

external resonator that supports a tuning range of

950 to 1473 MHz. The higher range VCO requires a

similar resonator with inductor values designed to

support the range of 1390 to 2150 MHz. A typical

lumped-element resonator circuit incorporating

varactor tuning is shown in the following figure:

+5

Vtune

10 kΩ

BB835

12pF

12pF

10 kΩ

L2 L2

47 Ω

L1

L1

47 Ω

29 High

28

32 Low

C1

33

5503

Note: A separate resonator circuit is required for

each oscillator

PLL Synthesizer

The synthesizer derives its reference from a source

which can be either an externally derived clock or an

external crystal coupled to the internal oscillator.

This source drives a programmable reference divider

with 15 preset divide ratios from 2 to 320. This

divider output provides the PLL reference by driving

one input of a phase/frequency detector. The VCO

output drives a divider chain incorporating a variable

modulus prescaler and divider. The divider is

programmed by a 17-bit control word. This divider

chain output drives the other input of the

phase/frequency detector.

Loop Filter

The phase/frequency detector interface consists of

two ports, FILN and EON. The EON drives the base

of an external NPN transistor, and the FILN provides

a feedback path for the loop filter elements. The

external transistor permits VCO tune voltages of

greater than 30V and also provides the final stage of

the loop amplifier. Below is shown a typical loop

filter:

FILN

EON

1000pF

10 k

+28V

10 kW

0.1 F

Vtune

Q1

2

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