ISP1583BS 데이터 시트보기 (PDF) - NXP Semiconductors.

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ISP1583BS

Hi-Speed USB peripheral controller

NXP Semiconductors. 

NXP Semiconductors

ISP1583

Hi-Speed USB peripheral controller

8.13 Interrupt

8.13.1 Interrupt output pin

The Interrupt Configuration register of the ISP1583 controls the behavior of the INT output

pin. The polarity and signaling mode of the INT pin can be programmed by setting bits

INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see Table 28. Bit

GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT; see Table 25.

Default settings after reset are active LOW and level mode. When pulse mode is selected,

a pulse of 60 ns is generated when the OR-ed combination of all interrupt bits changes

from logic 0 to logic 1.

Figure 5 shows the relationship between interrupt events and pin INT.

Each of the indicated USB and DMA events is logged in a status bit of the Interrupt

register and the DMA Interrupt Reason register, respectively. Corresponding bits in the

Interrupt Enable register and the DMA Interrupt Enable register determine whether an

event will generate an interrupt.

Interrupts can be masked globally by means of bit GLINTENA of the Mode register.

Field CDBGMOD[1:0] of the Interrupt Configuration register controls the generation of INT

signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt Configuration register

controls the generation of INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the

Interrupt Configuration register controls the generation of INT signals for the OUT pipe;

see Table 29.

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

© NXP B.V. 2008. All rights reserved.

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