THC63LVD103 데이터 시트보기 (PDF) - THine Electronics, Inc.
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THC63LVD103 Datasheet PDF : 12 Pages
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THC63LVD103 _Rev2.2
Switching Characteristics
Symbol
tTCIT
tTCP
tTCH
tTCL
tTCD
tTS
tTH
tLVT
tTOP1
Parameter
CLK IN Transition time
CLK IN Period
CLK IN High Time
CLK IN Low Time
CLK IN to TCLK+/- Delay
TTL Data Setup to CLK IN
TTL Data Hold from CKL IN
LVDS Transition Time
Output Data Position0
tTOP0 Output Data Position1
tTOP6 Output Data Position2
tTOP5 Output Data Position3
tTOP4 Output Data Position4
tTOP3 Output Data Position5
tTOP2
tTPLL
Output Data Position6
Phase Lock Loop Set
AC Timing Diagrams
Min.
VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C
Typ.
Max.
Units
5.0
ns
7.4
0.35tTCP
0.35tTCP
2.5
0.5tTCP
0.5tTCP
3tTCP
125.0
ns
0.65tTCP
ns
0.65tTCP
ns
ns
ns
0
ns
0.6
1.5
ns
-0.2
0.0
+0.2
ns
t--T----C---P- – 0.2
7
-t-T----C---P-
-t-T----C---P- + 0.2
ns
7
7
2t--T----C---P- – 0.2
7
2 -t-T----C---P-
7
2-t-T----C---P- + 0.2
ns
7
3t--T----C---P- – 0.2
7
3 -t-T----C---P-
7
3-t-T----C---P- + 0.2
ns
7
4t--T----C---P- – 0.2
7
4 -t-T----C---P-
7
4-t-T----C---P- + 0.2
ns
7
5t--T----C---P- – 0.2
7
5 -t-T----C---P-
7
5-t-T----C---P- + 0.2
ns
7
6t--T----C---P- – 0.2
7
6 -t-T----C---P-
7
6-t-T----C---P- + 0.2
ns
7
10.0
ms
TTL Input
LVDS Output
Vdiff=(TA+)-(TA-)
TA+
5pF 100Ω
TA-
LVDS Output Load
CLK IN
90%
10%
tTCIT
Vdiff
80%
20%
tLVT
90%
10%
tTCIT
80%
20%
tLVT
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