M48Z02-150PC1_99 데이터 시트보기 (PDF) - STMicroelectronics
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M48Z02-150PC1_99 Datasheet PDF : 12 Pages
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M48Z02
M48Z12
16 Kbit (2Kb x 8) ZEROPOWER® SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z02: 4.50V ≤ VPFD ≤ 4.75V
– M48Z12: 4.20V ≤ VPFD ≤ 4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2K x 8 SRAMs
DESCRIPTION
The M48Z02/12 ZEROPOWER® RAM is a 2K x 8
non-volatile static RAM which is pin and functional
compatible with the DS1220.
A special 24 pin 600mil DIP CAPHAT™ package
houses the M48Z02/12 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
The M48Z02/12 button cell has sufficient capacity
and storage life to maintain data and clock function-
ality for an accumulated time period of at least 10
years in the absence of power over the operating
temperature range.
Table 1. Signal Names
A0-A10
Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
24
1
PCDIP24 (PC)
Battery CAPHAT
Figure 1. Logic Diagram
VCC
11
A0-A10
8
DQ0-DQ7
W
M48Z02
M48Z12
E
G
VSS
AI01186
May 1999
1/12
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