FM24CL64B(2014) 데이터 시트보기 (PDF) - Cypress Semiconductor

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FM24CL64B
(Rev.:2014)

64-Kbit (8K × 8) Serial (I2C) F-RAM

Cypress Semiconductor 

FM24CL64B

Power Cycle Timing

Over the Operating Range

Parameter

Description

Min

tPU

Power-up VDD(min) to first access (START condition)

1

tPD

Last access (STOP condition) to power-down (VDD(min))

0

tVR [8, 9]

VDD power-up ramp rate

30

tVF [8, 9]

VDD power-down ramp rate

30

Figure 16. Power Cycle Timing

VDD

VDD(min)

tVR

tPU

VDD(min)

tVF

tPD

SDA

I2C START

I2C STOP

Max Unit

–

ms

–

µs

–

µs/V

–

µs/V

Note

8. Slope measured at any point on the VDD waveform.

9. Guaranteed by design.

Document Number: 001-84458 Rev. *D

Page 13 of 19

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