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74VCX16373

LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS

STMicroelectronics 

74VCX16373

LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE)

WITH 3.6V TOLERANT INPUTS AND OUTPUTS

s 3.6V TOLERANT INPUTS AND OUTPUTS

s HIGH SPEED :

tPD = 3.0 ns (MAX.) at VCC = 3.0 to 3.6V

tPD = 3.4 ns (MAX.) at VCC = 2.3 to 2.7V

tPD = 6.8 ns (MAX.) at VCC = 1.8V

s POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24mA (MIN) at VCC = 3.0V

|IOH| = IOL = 18mA (MIN) at VCC = 2.3V

|IOH| = IOL = 6mA (MIN) at VCC = 1.8V

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 1.8V to 3.6V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 16373

s LATCH-UP PERFORMANCE EXCEEDS

300mA (JESD 17)

s ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

DESCRIPTION

The 74VCX16373 is a low voltage CMOS 16 BIT

D-TYPE LATCH with 3 STATE OUTPUTS NON

INVERTING fabricated with sub-micron silicon

gate and five-layer metal wiring C2MOS

technology. It is ideal for low power and very high

speed 1.8 to 3.6V applications; it can be interfaced

to 3.6V signal environment for both inputs and

outputs.

These 16 bit D-TYPE latches are bite controlled

by two latch enable inputs (nLE) and two output

enable inputs (OE).

While the nLE input is held at a high level, the nQ

outputs will follow the data input precisely.

When the nLE is taken low, the nQ outputs will be

in a normal logic state (high or low logic level) and

while high level the outputs will be in a high

impedance state.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

TSSOP

ORDER CODES

PACKAGE

TSSOP

TUBE

PIN CONNECTION

T&R

74VCX16373TTR

February 2003

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