MFRC52201HN1/TRAYBM_10 데이터 시트보기 (PDF) - NXP Semiconductors.
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MFRC52201HN1/TRAYBM_10 Datasheet PDF : 96 Pages
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NXP Semiconductors
MFRC522
Contactless reader IC
Table 26. ComIEnReg register bit descriptions
Bit Symbol Value Description
7 IRqInv
1
signal on pin IRQ is inverted with respect to the Status1Reg register’s
IRq bit
0
signal on pin IRQ is equal to the IRq bit; in combination with the
DivIEnReg register’s IRqPushPull bit, the default value of logic 1 ensures
that the output level on pin IRQ is 3-state
6 TxIEn
-
allows the transmitter interrupt request (TxIRq bit) to be propagated to
pin IRQ
5 RxIEn
-
allows the receiver interrupt request (RxIRq bit) to be propagated to pin
IRQ
4 IdleIEn -
allows the idle interrupt request (IdleIRq bit) to be propagated to pin IRQ
3 HiAlertIEn -
allows the high alert interrupt request (HiAlertIRq bit) to be propagated to
pin IRQ
2 LoAlertIEn -
allows the low alert interrupt request (LoAlertIRq bit) to be propagated to
pin IRQ
1 ErrIEn
-
allows the error interrupt request (ErrIRq bit) to be propagated to pin IRQ
0 TimerIEn -
allows the timer interrupt request (TimerIRq bit) to be propagated to pin
IRQ
9.3.1.4 DivIEnReg register
Control bits to enable and disable the passing of interrupt requests.
Table 27.
Bit
Symbol
Access
DivIEnReg register (address 03h); reset value: 00h bit allocation
7
65
4
3
2
IRQPushPull reserved MfinActIEn reserved
CRCIEn
R/W
-
R/W
-
R/W
10
reserved
-
Table 28. DivIEnReg register bit descriptions
Bit Symbol
Value Description
7
IRQPushPull 1
pin IRQ is a standard CMOS output pin
0
pin IRQ is an open-drain output pin
6 to 5 reserved
-
reserved for future use
4
MfinActIEn -
allows the MFIN active interrupt request to be propagated to
pin IRQ
3
reserved
-
reserved for future use
2
CRCIEn
-
allows the CRC interrupt request, indicated by the DivIrqReg
register’s CRCIRq bit, to be propagated to pin IRQ
1 to 0 reserved
-
reserved for future use
9.3.1.5 ComIrqReg register
Interrupt request bits.
Table 29.
Bit
Symbol
Access
ComIrqReg register (address 04h); reset value: 14h bit allocation
7
6
5
4
3
2
1
Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq
W
D
D
D
D
D
D
0
TimerIRq
D
MFRC522_34
Product data sheet
PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.4 — 5 March 2010
112134
© NXP B.V. 2010. All rights reserved.
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