Block Diagram
VIN
ZXLD1360Q
D1
RS
`L1
5 VIN
4 ISENSE
1 LX
C1
4.7µF
5V
Voltage
regulator
R1
0.2V
ADJ
3
R4 R5
200k 20k
R2
Low voltage
detector
MN
D1
1.25V
GND
2
R3
1.35V
Figure 1 Block diagram – With Pin Connections
Pin Descriptions
Name
LX
GND
ADJ
ISENSE
VIN
Pin No.
1
2
3
4
5
Description
Drain of NDMOS switch
Ground (0V)
Multi-function On/Off and brightness control pin:
• Leave floating for normal operation (VADJ = VREF = 1.25V giving nominal average output current
IOUTnom = 0.1/RS)
• Drive to voltage below 0.2V to turn off output current
• Drive with DC voltage (0.3V < VADJ < 2.5V) to adjust output current from 25% to 200% of IOUTnom
• Drive with PWM signal from open-collector or open-drain transistor, to adjust output current
• Adjustment range 25% to 100% of IOUTnom for f>10kHz and 1% to 100% of IOUTnom for f < 500Hz
• Connect a capacitor from this pin to ground to increase soft-start time
(Default soft-start time = 500µs. Additional soft-start time is approximately 500µs/nF)
Connect resistor RS from this to VIN to define nominal average output current IOUTnom=0.1/RS
(Note: RSMIN=0.1V with ADJ pin open circuit)
Input Voltage (7V to 30V)
Decouple to ground with 4.7µF of higher X7R ceramic capacitor close to device
ZXLD1360Q
Document number: DS37115 Rev. 1 - 2
2 of 22
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September 2015
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