74ABT841(2010) 데이터 시트보기 (PDF) - NXP Semiconductors.
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74ABT841 Datasheet PDF : 15 Pages
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NXP Semiconductors
74ABT841
10-bit bus interface latch; 3-state
VI
Dn
GND
VM
VM
tsu(H) th(H)
VM
VM
tsu(L) th(L)
VI
LE
VM
GND
VM
001aae918
Fig 8.
VM = 1.5 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Data set-up and hold times
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
tW
90 %
VM
10 %
tr
tf
90 %
VM
10 %
tW
001aai298
VI
G
VCC
VO
DUT
RT
a. Input pulse definition
b. Test circuit
Fig 9.
Test data and VEXT levels are given in Table 8.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Test circuit for measuring switching times
VEXT
RL
CL
RL
mna616
Table 8.
Input
VI
3.0 V
Test data
fI
1 MHz
tW
500 ns
tr, tf
≤ 2.5 ns
Load
CL
50 pF
RL
500 Ω
VEXT
tPHL, tPLH
open
tPZH, tPHZ
open
tPZL, tPLZ
7.0 V
74ABT841_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
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