MC100EL39 데이터 시트보기 (PDF) - ON Semiconductor

부품명

상세내역

제조사

MC100EL39

5VECL ÷2/4, ÷4/6 Clock Generation Chip

ON Semiconductor 

MC100EL39

VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE

20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10

VCC EN

CLK CLK VBB MR VCC NC

NOTE: All VCC pins are tied together on the die.

Warning: All VCC and VEE pins must be externally connected to

Power Supply to guarantee proper operation.

Figure 1. Pinout: SOIC−20 (Top View)

DIVSELa

CLK

CLK

Q0

P2/4

Q0

R

Q1

Q1

Table 1. PIN DESCRIPTION

Pin

Function

CLK, CLK

EN

MR

Q0, Q0; Q1, Q1

Q2, Q2; Q3, Q3

DIVSELa,

DIVSELb

VBB

VCC

VEE

NC

ECL Diff Clock Inputs

ECL Sync Enable

ECL Master Reset

ECL Diff ÷2/4 Outputs

ECL Diff ÷4/6 Outputs

ECL Frequency Select Input

ECL Frequency Select Input

Reference Voltage Output

Positive Supply

Negative Supply

No Connect

Table 2. FUNCTION TABLE

Function

CLK*

EN*

MR*

Divide

Z

L

L

Hold Q0−3

ZZ

H

L

Reset Q0−3

X

X

H

Z = Low-to-High Transition

ZZ = High-to-Low Transition

*Pin will default low when left open.

EN

P4/6

R

MR

DIVSELb

Figure 2. Logic Diagram

Q2

DIVSELa**

Q0, Q1 Outputs

Q2

0

1

Q3

Divide by 2

Divide by 4

DIVSELb**

Q2, Q3 Outputs

Q3

0

Divide by 4

1

Divide by 6

**Pin will default low when left open.

http://onsemi.com

2

Share Link: