MCM69P735ZP2.5 데이터 시트보기 (PDF) - Motorola => Freescale

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MCM69P735ZP2.5

128K x 36 Bit Pipelined BurstRAM™ Synchronous Fast Static RAM

Motorola => Freescale 

NON–BURST SYNCHRONOUS OPERATION

Although this BurstRAM has been designed for PowerPC–

based and other high end MPU–based systems, these

SRAMs can be used in other high speed L2 cache or

memory applications that do not require the burst address

feature. Most L2 caches designed with a synchronous inter-

face can make use of the MCM69P735. The burst counter

feature of the BurstRAM can be disabled, and the SRAM can

be configured to act upon a continuous stream of addresses.

See Figure 5.

CONTROL PIN TIE VALUES (H ≥ VIH, L ≤ VIL)

Non–Burst

ADSP ADSC ADV SE1 LBO

Sync Non–Burst,

Pipelined SRAM

H

L

H

L

X

NOTE: Although X is specified in the table as a don’t care, the pin

must be tied either high or low.

K

ADDR

A

B

C

D

W

E

F

G

H

G

DQ

Q(A)

Q(B)

Q(C)

Q(D)

D(E)

D(F)

D(G)

D(H)

READS

Figure 5. Configured as Non–Burst Synchronous SRAM

WRITES

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix

MCM 69P735 XX X X

Blank = Trays, R = Tape and Reel

Part Number

Speed (2.5 = 2.5 ns, 3 = 3.0 ns, 3.5 = 3.5 ns)

Package (ZP = PBGA)

Full Part Numbers — MCM69P735ZP2.5 MCM69P735ZP3

MCM69P735ZP2.5R MCM69P735ZP3R

MCM69P735ZP3.5

MCM69P735ZP3.5R

MOTOROLA FAST SRAM

MCM69P735

15

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