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MC14LC5480SD 데이터 시트보기 (PDF) - Freescale Semiconductor

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MC14LC5480SD
Freescale
Freescale Semiconductor Freescale
MC14LC5480SD Datasheet PDF : 24 Pages
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Freescale Semiconductor, Inc.
DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC
(VDD = + 5 V ± 5%, VSS = 0 V, All Digital Signals Referenced to VSS, TA = – 40 to + 85°C, CL = 150 pF, Unless Otherwise Noted)
Ref.
No.
Characteristics
Min
Typ
Max
Unit
1 Master Clock Frequency for MCLK
256
kHz
512
1536
1544
2048
2560
4096
1 MCLK Duty Cycle for 256 kHz Operation
45
55
%
2 Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater)
50
ns
3 Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater)
50
ns
4 Rise Time for All Digital Signals
50
ns
5 Fall Time for All Digital Signals
50
ns
6 Setup Time from MCLK Low to FST High
50
ns
7 Setup Time from FST High to MCLK Low
50
ns
8 Bit Clock Data Rate for BCLKT or BCLKR
64
4096
kHz
9 Minimum Pulse Width High for BCLKT or BCLKR
50
ns
10 Minimum Pulse Width Low for BCLKT or BCLKR
50
ns
11 Hold Time from BCLKT (BCLKR) Low to FST (FSR) High
20
ns
12 Setup Time for FST (FSR) High to BCLKT (BCLKR) Low
80
ns
13 Setup Time from DR Valid to BCLKR Low
0
ns
14 Hold Time from BCLKR Low to DR Invalid
50
ns
LONG FRAME SPECIFIC TIMING
15 Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low
50
ns
16 Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data
60
ns
17 Delay Time from BCLKT High to DT for Valid Chord and Step Bit Data
60
ns
18 Delay Time from the Later of the 8th BCLKT Falling Edge, or the Falling Edge
10
60
ns
of FST to DT Output High Impedance
19 Minimum Pulse Width Low for FST or FSR
50
ns
SHORT FRAME SPECIFIC TIMING
20 Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low
50
ns
21 Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low
50
ns
22 Delay Time from BCLKT High to DT Data Valid
10
60
ns
23 Delay Time from the 8th BCLKT Low to DT Output High Impedance
10
60
ns
For More Information On This Product,
Go to: www.freescale.com

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