MAX11044ECB(2010) 데이터 시트보기 (PDF) - Maxim Integrated
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MAX11044ECB Datasheet PDF : 20 Pages
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4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
PIN
TQFP
TQFN
42
37
44
39
47
42
50
45
61
52
62
53
63
54
64
55
—
—
Pin Description (continued)
NAME
CH4
CH5
CH6
CH7
WR
CS
RD
DB15
EP
FUNCTION
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are
loaded on the rising edge of WR.
Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC.
Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD
advances the channel output on the data bus.
16-Bit Parallel Data Bus Digital Out Bit 15
Exposed Pad. Internally connected to AGND. Connect to a large ground plane to
maximize thermal performance. Not intended as an electrical connection point.
Detailed Description
The MAX11044/MAX11045/MAX11046 are fast, low-
power ADCs that combine 4, 6, or 8 independent ADC
channels in a single IC. Each channel includes simulta-
neously sampling independent T/H circuitry that pre-
serves relative phase information between inputs
making the MAX11044/MAX11045/MAX11046 ideal for
motor control and power monitoring. The MAX11044/
MAX11045/MAX11046 are available with ±5V input
ranges that feature ±20mA overrange, fault-tolerant
inputs. The MAX11044/MAX11045/MAX11046 operate
with a single 4.75V to 5.25V supply. A separate 2.7V to
5.25V supply for digital circuitry makes the devices
compatible with low-voltage processors.
The MAX11044/MAX11045/MAX11046 perform conver-
sions for all channels in parallel by activating indepen-
dent ADCs. Results are available through a high-speed,
20MHz, parallel data bus after a conversion time of 3μs
following the end of a sample. The data bus is bidirec-
tional and allows for easy programming of the configu-
ration register. The MAX11044/MAX11045/MAX11046
feature a reference buffer, which is driven by an internal
bandgap reference circuit (VREFIO = 4.096V). Drive
REFIO with an external reference or bypass with 0.1μF
capacitor to ground when using the internal reference.
Analog Inputs
Track and Hold (T/H)
To preserve phase information across all channels,
each input includes a dedicated T/H circuitry. The input
tracking circuitry provides a 4MHz small-signal band-
width, enabling the device to digitize high-speed tran-
sient events and measure periodic signals with band-
widths exceeding the ADC’s sampling rate by using
undersampling techniques. Use anti-alias filtering to
avoid high-frequency signals being aliased into the fre-
quency band of interest.
Input Range and Protection
The full-scale analog input voltage is a product of the ref-
erence voltage. For the MAX11044/MAX11045/
MAX11046, the full-scale input is bipolar in the range of:
±(VREFIO
x
5)
4.096
When in external reference mode, drive VREFIO with a
3.0V to 4.25V source, resulting in an input range of
±3.662V to ±5.188V, respectively.
All analog inputs are fault-protected to up to ±20mA.
The MAX11044/MAX11045/MAX11046 include an input
clamping circuit that activates when the input voltage at
the analog input is above (VAVDD + 300mV) or below
–(VAVDD + 300mV). The clamp circuit remains high
impedance while the input signal is within the range of
±VAVDD and draws little or almost no current. However,
when the input signal exceeds ±VAVDD, the clamps
begin to turn on and shunt current to/from the AVDD
supply. Consequently, to obtain the highest accuracy,
ensure that the input voltage does not exceed ±VAVDD.
Note that the input clamp circuit also has a small
amount of hysteresis and once triggered remains
engaged, shunting current to/from AVDD until the input
returns to within the convertible range by several hun-
dredths of a volt. This effect can cause some errors at
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