CL10K50V 데이터 시트보기 (PDF) - Clear Logic
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CL10K50V Datasheet PDF : 16 Pages
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LIBERATOR CL10K50V
AC Electrical Specifications cont.
Logic Element Timing Parameters[5]
Speed: -1
Symbol
Parameter
Min Max
tLUT Look-up Table Delay for Data-in
0.9
tCLUT Look-up Table Delay for Carry-in
0.1
tRLUT
Look-up Table Delay for LE Register
Feedback
0.5
tPACKED Data-in to Packed Register Delay
0.4
tEN LE Register Enable Delay
0.7
tCICO Carry-in to Carry-out Delay
0.2
tCGEN Data-in to Carry-out Delay
0.8
tCGENR
LE Register Feedback to Carry-out
Delay
0.4
tCASC Cascade Chain Routing Ddelay
0.7
tC LE Register Control Signal Delay
0.3
tCO LE Register Clock-to-output Delay
0.5
tCOMB Combinatorial Delay
0.4
tSU LE Register Setup Time Before Clock 0.8
tH LE Register Hold Time After Clock
0.5
tPRE LE Register Preset Delay
0.8
tCLR LE Register Clear Delay
0.8
tCH Clock High Time
2.0
tCL Clock Low Time
2.0
Speed: -2
Min Max
1.0
0.5
0.8
0.4
0.9
0.2
0.7
0.3
0.7
1.0
0.7
0.4
1.6
0.8
0.4
0.4
4.0
4.0
Speed: -3
Min Max
1.3
0.6
0.9
0.5
1.1
0.2
0.8
0.3
0.8
1.3
0.9
0.5
2.2
1.0
0.5
0.5
4.0
4.0
Speed: -4
Min Max Unit
1.6 ns
0.6 ns
1.0 ns
0.7 ns
1.4 ns
0.3 ns
1.2 ns
0.4 ns
0.9 ns
1.5 ns
1.0 ns
0.6 ns
2.5
ns
1.4
ns
0.5 ns
0.5 ns
4.0
ns
4.0
ns
10KA tbl 08A
Page 10
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