CL10K50V 데이터 시트보기 (PDF) - Clear Logic
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CL10K50V Datasheet PDF : 16 Pages
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LIBERATOR CL10K50V
AC Electrical Specifications
I/O Element Timing Parameters [5]
Speed: -1
Symbol
Parameter
Min Max
Speed: -2
Min Max
Speed: -3
Min Max
Speed: -4
Min Max Unit
tIOD IOE Register Data Delay
1.2
1.6
1.9
2.1 ns
tIOC IOE Register Control Signal Delay
0.3
0.4
0.5
0.5 ns
tIOCO IOE Register Clock to Output Delay
0.3
0.3
0.4
0.4 ns
tIOCOMB IOE Combinatorial Delay
0.0
0.0
0.0
0.0 ns
tIOSU IOE Register Setup TIme Before Clock 2.8
2.8
3.4
3.9
ns
tIOH IOE Register Hold Time After Clock
0.7
0.8
1.0
1.4
ns
tIOCLR
tOD1
IOE Register Clear Delay
Output Buffer and Pad Delay
Slow Slew Rate = off,
VCCIO = 5.0v, CL = 35 pF
0.5
0.6
0.7
0.7 ns
2.8
3.2
3.9
4.7 ns
Output Buffer and Pad Delay
tOD3 Slow Slew Rate = off,
VCCIO = 5.0v, CL = 35 pF
6.5
6.9
7.6
8.4 ns
tZX Output Buffer Disable Delay[6]
2.8
3.1
3.8
4.6 ns
Output Buffer Disable Delay
tZX1 Slow Slew Rate = off, VCCIO = 5.0v,
2.8
3.1
3.8
4.6 ns
CL = 35 pF[6]
Output Buffer Disable Delay
tZX3 Slow Slew Rate = off,
VCCIO = 5.0v, CL = 35 pF[6]
6.5
6.8
7.5
8.3 ns
tINREG
IOE Input Pad and Buffer to IOE
Register Delay
5.0
5.7
7.0
9.0 ns
tIOFD IOE Register Feedback Delay
1.5
tINCOMB
IOE Input Pad and Buffer to
Interconnect Delay
1.5
External Timing Parameters[4] Speed: -1
Symbol
Parameter
Min Max
1.9
1.9
Speed: -2
Min Max
2.3
2.3
Speed: -3
Min Max
2.7 ns
2.7 ns
10KA tbl 06A
Speed -4
Min Max Unit
Register to Register Delay via Four
tDRR LEs, Three Row Interconnects, and
Four Local Interconnects
11.2
14.0
17.2
21.1 ns
tINSU
Setup Time with Global Clock at IOE
Regis ter
5.5
4.2
5.2
6.9
ns
tINH
Hold time with Global Clock at IOE
Regis ter
0.0
0.0
0.0
0.0
ns
tOUTCO Output Data Hold Time After Clock
2.0 5.9 2.0 7.8 2.0 9.5 2.0 11.1 ns
10KA tbl 07A
Page 9
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